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參數(shù)資料
| 型號： | CYDM064B16 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1.8V 4K/8K/16K x 16 MoBL㈢ Dual-Port Static RAM |
| 中文描述： | 1.8 4K/8K/16K㈢× 16的MoBL雙端口靜態(tài)存儲器 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 583K |
| 代理商： | CYDM064B16 |
CYDM256B16
CYDM128B16
CYDM064B16
Document #: 001-00217 Rev. *E
Page 12 of 25
7
AC Test Loads and Waveforms
Switching Characteristics for V
CC
= 1.8V
Over the Operating Range
[23]
Parameter
Description
CYDM256B16,
CYDM128B16,
CYDM064B16
CYDM256B16,
CYDM128B16,
CYDM064B16
Unit
-40
-55
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE[24]
t
DOE
t
LZOE[25, 26, 27]
t
HZOE[25, 26, 27]
t
LZCE[25, 26, 27]
t
HZCE[25, 26, 27]
t
PU[27]
t
PD[27]
t
ABE[24]
Write Cycle
Read Cycle Time
40
55
ns
Address to Data Valid
40
55
ns
Output Hold From Address Change
5
5
ns
CE LOW to Data Valid
40
55
ns
OE LOW to Data Valid
25
30
ns
OE Low to Low Z
5
5
ns
OE HIGH to High Z
15
25
ns
CE LOW to Low Z
5
5
ns
CE HIGH to High Z
15
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
40
55
ns
Byte Enable Access Time
40
55
ns
t
WC
t
SCE[24]
t
AW
t
HA
Write Cycle Time
40
55
ns
CE LOW to Write End
30
45
ns
Address Valid to Write End
30
45
ns
Address Hold From Write End
0
0
ns
Notes:
23.Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
CC
/2, input pulse levels of 0 to V
CC
, and output loading of the specified
I
/I
and 30-pF load capacitance.
24.To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
SCE
time.
25.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
26.Test conditions used are Load 3.
27.This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform
1.8V
GND
90%
90%
10%
10%
ALL INPUT PULSES
(a) Normal Load
R1
3.0V/2.5V/1.8V
OUTPUT
R2
C = 30 pF
V
TH
= 0.8V
OUTPUT
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
R1
R2
3.0V/2.5V/1.8V
OUTPUT
R
TH
= 6 k
≤
3 ns
≤
3 ns
including scope and jig)
3.0V/2.5V
1022
792
1.8V
13500
10800
R1
R2
C = 30 pF
C = 5 pF
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYDM064B16_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL? Dual-Port Static RAM |
| CYDM064B16_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL Dual-Port Static RAM |
| CYDM064B16_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1.8V 4K/8K/16K x 16 MoBL? Dual-Port Static RAM |
| CYDM064B16-40BVXI | 功能描述:靜態(tài)隨機存取存儲器 64K 4Kx16 MoBL Dual Port IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CYDM064B16-40BVXIT | 功能描述:IC SRAM 64KBIT 40NS 100VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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