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參數(shù)資料
| 型號： | CYC1021B-12VC |
| 英文描述： | IC-1MB CMOS SRAM |
| 中文描述： | 集成電路1MB的CMOS SRAM的 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 308K |
| 代理商： | CYC1021B-12VC |
CY7C1021B
3
AC Test Loads and Waveforms
1021B-3
1021B-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R 481
R 481
R2
255
R2
255
167
Equivalent to:
THéVENIN
EQUIVALENT
1.73V
30 pF
Rise Time: 1 V/ns
Fall Time :1 V/ns
Switching Characteristics
[5]
Over the Operating Range
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
Description
7C1021B-9
Min.
7C1021B-10
Min.
7C1021B-12
Min.
7C1021B-15
Min.
7C1021B-20
Min.
Unit
Max.
Max.
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
9
10
12
15
20
ns
ns
ns
9
10
12
15
20
3
3
3
3
3
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Shaded areas contain preliminary information.
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
6.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
7.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8.
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9
5
10
5
12
6
15
7
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
5
5
6
7
9
3
3
3
3
3
5
5
6
7
9
0
0
0
0
0
9
5
10
5
12
6
15
7
20
9
0
0
0
0
0
5
5
6
7
9
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
9
8
7
0
0
7
5
0
3
10
8
7
0
0
7
5
0
3
12
9
8
0
0
8
6
0
3
15
10
10
0
0
10
8
0
3
20
12
12
0
0
12
10
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
7
9
7
7
8
9
12
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