參數(shù)資料
型號: CY9C6264-70SNI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 存儲器
英文描述: 8K x 8 Magnetic Nonvolatile CMOS RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PDSO28
封裝: 0.300 INCH, SOIC-28
文件頁數(shù): 7/12頁
文件大?。?/td> 377K
代理商: CY9C6264-70SNI
PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 7 of 12
Write Cycle No. 2 (CE
1
Or CE
2
Controlled)
[10, 15, 16]
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15, 16, 18]
Truth Table
CE
1
H
CE
2
L
WE
OE
V
CC
Inputs/Outputs
Mode
Power
X
X
4.5–5.5V High-Z
Deselect/Power-down
Standby (I
SB
)
Standby (I
SB
)
Standby (I
SB
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
Active (I
CC
)
H
H
X
X
4.5–5.5V High-Z
Deselect/Power-down
L
L
X
X
4.5–5.5V High-Z
Deselect/Power-down
L
H
H
L
4.5–5.5V Data Out
Read
L
H
L
X
4.5–5.5V Data In
Write
L
H
H
H
4.5–5.5V High-Z
Deselect, Output Disabled
X
X
X
X
< 4.0V
Inputs = X, Outputs = High-Z
Write Inhibit
Note:
18.If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE HIGH, the outputs remain in high-impedance state.
Switching Waveforms
(continued)
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE1
WE
DATA I/O
ADDRESS
CE
1
DATA IN VALID
t
SCE2
CE
2
DATA I/O
ADDRESS
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
CE
1
WE
t
HZWE
DATA IN VALID
NOTE 17
CE
2
t
SCE1
t
SCE2
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