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| 型號(hào)： | CY9C6264-70SNI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | CY9C6264-70SNI |
PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 5 of 12
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
CY9C6264-70
Min.
Unit
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW to Data Valid
CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE
1
LOW to Low-Z
[8]
CE
2
HIGH to Low-Z
[8]
CE
1
HIGH to High-Z
[8, 9]
CE
2
LOW to High-Z
[8, 9]
CE
1
LOW to Power-up
CE
2
HIGH to Power-up
CE
1
HIGH to Power-down
CE
2
LOW to Power-down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
5
70
70
35
5
25
5
5
25
t
PU
0
ns
t
PD
70
ns
Write Cycle
[10, 11]
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE1
is less than t
LZCE1
, t
HZCE2
is less than t
LZCE2
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for
any given device.
9. t
, t
, and t
are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
10.The internal Write time of the memory is defined by the overlap of CE
LOW or CE
HIGH and WE LOW. Both signals must be LOW to initiate a Write and either
signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum write pulse width for Write cycle #3 (WE-controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Write Cycle Time
CE
1
LOW to Write End
CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
70
60
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
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| CY9C6264-70ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
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