- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379098 > CY9C6264-70SNI (CYPRESS SEMICONDUCTOR CORP) 8K x 8 Magnetic Nonvolatile CMOS RAM PDF資料下載
參數(shù)資料
| 型號： | CY9C6264-70SNI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 存儲器 |
| 英文描述： | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 377K |
| 代理商： | CY9C6264-70SNI |
PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 2 of 12
Overview
The CY9C6264 is a byte-wide MRAM memory. The memory
array is logically organized as 8,192 × 8 and is accessed using
an industry standard parallel asynchronous SRAM-like
interface. The CY9C6264 is inherently nonvolatile and offers
write protect during sudden power loss. Functional operation
of the MRAM is otherwise similar to SRAM-type devices.
Memory Architecture
Users access 8,192 memory locations each with eight data
bits through a parallel interface. Internally, the memory array
is organized into 8 blocks of 128 rows x 64 columns each.
The access and cycle time are the same for Read and Write
memory operations. Unlike an EEPROM or Flash, it is not
necessary to poll the device for a ready condition since writes
occur at bus speed.
Memory Operation
The CY9C6264 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the MRAM performance is superior. For users
familiar with EEPROM, Flash, and FeRAM, the obvious differ-
ences result from higher write performance of MRAM
technology and much higher write endurance.
All memory array bits are set to logic “1” at the time of
shipment.
Read Operation
A read cycle begins whenever WE (Write Enable) is inactive
(HIGH) and CE
1
(Chip Enable) and OE (Output Enable) are
active LOW while CE
2
is active HIGH. The unique address
specified by the 13 address inputs (A
0
–A
12
) defines which of
the 8,192 bytes of data is to be accessed. Valid data will be
available at the eight output pins within t
AA
(access time) after
the last address input is stable, providing that CE
1
or CE
2
and
OE access times are also satisfied. If CE
1
or CE
2
and OE
access times are not satisfied, the data access must be
measured from the later-occurring signal (CE
1
, CE
2
or OE)
and the limiting parameter is either t
ACE1
for CE
1
, t
ACE2
for
CE
2
, or t
DOE
for the OE rather than address access.
Write Cycle
The CY9C6264 initiates a Write cycle whenever the WE and
CE
1
signals are active (LOW) or WE is LOW and CE
2
is HIGH,
after address inputs are stable. The later occurring falling edge
of CE
1
(rising in case of CE
2
) or WE will determine the start of
the Write cycle. The Write cycle is terminated by the earlier
rising edge of CE
1
(falling edge in case of CE
2
) or WE. All
address inputs must be kept valid throughout the Write cycle.
The OE control signal should be kept inactive (HIGH) during
Write cycles to avoid bus contention. However, if the output
drivers are enabled (CE
1
or CE
2
and OE active), WE will
disable the outputs in t
HZWE
from the WE falling edge.
Unlike other nonvolatile memory technologies, there is no
Write delay with MRAM. The entire memory operation occurs
in a single bus cycle. Therefore, any operation including Read
or Write can occur immediately following a Write. Data Polling,
a technique used with EEPROMs to determine if the Write is
complete, is unnecessary. Page Write, a technique used to
enhance EEPROM Write performance, is also unnecessary
because of inherently fast Write cycle time for MRAM. The
total write time for the entire array is 0.575 ms.
Write Inhibit and Data Retention Mode
This feature protects against the inadvertent Write. The
CY9C6264 provides full functional capability for V
CC
greater
than 4.5V and Write-protects the device below 4.0V. Data is
maintained in the absence of V
CC
. During the power-up,
normal operation can resume 20
s after V
PFD
is reached.
Refer to page 8 for details.
Sudden Power Loss—“Brown out”
The nonvolatile RAM constantly monitors V
CC
. Should the
supply voltage decay below the operating range, the
CY9C6264 automatically write-protects itself, all inputs
become “don’t care,” and all outputs become high impedance.
Refer to page 8 for details.
Silicon Signature/Device ID
An extra 64 bytes of MRAM are available to the user for Device
ID. By raising A
7
to V
CC
+ 2.0V and by using address locations
00 (Hex) to 3F (Hex) on address pins A
6
, A
5
, A
4
, A
12
, A
11
, and
A
10
(MSB to LSB) respectively, the additional bytes may be
accessed in the same manner as the regular memory array
with 140ns read access time and 140ns write cycle time.
Writing the extra bytes of MRAM requires a longer address
setup to write start of 70 ns vs. the normal operating specifi-
cation of 0ns. Dropping A
7
from input high (V
CC
+ 2.0V) to <
V
CC
+ 0.5V max. returns the device to normal operation after
140-ns delay.
All User Space bits are set to logic “1” at the time of shipment.
Magnetic Shielding
CY9C6264 is protected from external magnetic fields through
the application of a “magnetic shield” that covers the entire
memory array.
Applications
Battery-backed SRAM (BBSRAM) Replacement
CY9C6264 is designed to replace (plug and play) existing
BBSRAM while eliminating the need for battery and V
CC
monitor IC, reducing cost and board space and improving
system reliability.
The cost associated with multiple components, assemblies,
and manufacturing overhead associated with battery-backed
SRAM is eliminated by using monolithic MRAM. CY9C6264
eliminates multiple assemblies, connectors, modules, field
maintenance, and environmental issues common with BB
SRAM. MRAM is a true nonvolatile RAM with high perfor-
mance, high endurance, and data retention.
Battery-backed SRAMs are forced to monitor V
CC
in order to
switch to the backup battery. Users that are modifying existing
designs to use MRAM in place of BBSRAM, can eliminate the
V
CC
controller IC along with the battery. MRAM performs this
function on-chip.
Address (MSB to LSB)
A
6
A
5
A
4
A
12
A
11
A
10
00h
01h
02h–3Fh
Description
Manufacturer ID
Device ID
User Space
ID
34h
41h
62 bytes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY9C6264-70PI | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70SI | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70SNC | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| CYD04S72V | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
| CYD04S72V-133BBC | FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY9C6264-70ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
| CY9C6264-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Magnetic Nonvolatile CMOS RAM |
| CYA10000 | 制造商:n/a 功能描述:_ |
| CYA-103 | 制造商:Hosa Technology 功能描述:3Ft Y Cable RCA To Dual RCA 制造商:HOSA 功能描述:3FT Y CABLE RCA TO DUAL RCA |
| CYA-110 | 制造商:Hosa Technology 功能描述:10Ft Y Cable RCA To Dual RCA 制造商:HOSA 功能描述:10FT Y CABLE RCA TO DUAL RCA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。