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參數(shù)資料
| 型號(hào)： | CY9C6264-70SNI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 存儲(chǔ)器 |
| 英文描述： | 8K x 8 Magnetic Nonvolatile CMOS RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 377K |
| 代理商： | CY9C6264-70SNI |
PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 6 of 12
Switching Waveforms
Read Cycle No. 1
[12, 13]
Read Cycle No. 2
[13, 14]
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
Notes:
12.Device is continuously selected. OE = V
IL
CE
1
= V
IL
or OE = V
IL
CE
2
= V
IH
.
13.WE is HIGH for Read cycle.
14.Address valid prior to or coincident with CE
1
transition LOW or CE
2
transition to HIGH.
15.Data I/O is high impedance if OE = V
.
16.If CE
goes HIGH Or CE
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
17.During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
1
HIGH
V
SUPPLY
CURRENT
CE
2
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
1
WE
OE
t
HZOE
DATA IN VALID
NOTE17
CE
2
t
SCE1
t
SCE2
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