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| 型號(hào)： | CY8C22213-24SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO20 |
| 封裝： | 0.300 INCH, MO-119, SOIC-20 |
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12. Sleep and Watchdog
CY8C22xxx Preliminary Data Sheet
74
Document No. 38-12009 Rev. *D
December 22, 2003
and is used to sequence system wakeup. It is also used to
periodically refresh the bandgap voltage during sleep.
12.1.2
Sleep Timer
The Sleep timer is a 15-bit, up counter clocked by the cur-
rently selected 32 kHz clock source, either the ILO or ECO.
This timer is always enabled. The exception to this is within
an ICE (in-circuit emulator) in debugger mode and the Stop
bit in the CPU_SCR0 is set; the Sleep timer is disabled, so
that the user will not get continual Watchdog resets when a
breakpoint is hit in the debugger environment.
If the associated Sleep timer interrupt is enabled, a periodic
interrupt to the CPU is generated based on the sleep inter-
val selected from the OSC_CR0 register. The Sleep timer
functionality does not need to be directly associated with
sleep state. It can be used as a general-purpose timer inter-
rupt regardless of sleep state.
The reset state of the Sleep timer is a count value of all
zeros. There are two ways to reset the Sleep timer. Any
hardware reset, i.e., power-on reset (POR), external reset
(XRES) or Watchdog reset (WDR) will reset the Sleep timer.
There is also a method that allows the user to reset the
Sleep timer in firmware. A write of 38h to the RES_WDT
register clears the Sleep timer. (Note: Any write to
RES_WDT register also clears the Watchdog timer.) Clear-
ing the Sleep timer may be done at anytime to synchronize
the Sleep timer operation to CPU processing. A good exam-
ple of this is after POR. The CPU hold-off due to voltage
ramp, etc., may be significant. In addition, a significant
amount of program initialization may be required. However,
the Sleep timer starts counting immediately after POR and
will be at an arbitrary count when user code begins execu-
tion. In this case, it may be desirable to clear the Sleep timer
before enabling the sleep interrupt initially, to ensure that the
first sleep period will be a full interval.
12.1.3
Sleep Bit
Sleep is initiated in firmware by setting the SLEEP bit (bit 3)
in the System Control register (CPU_SCR0). To wake up the
system, this register bit is cleared asynchronously by any
enabled interrupt. However, there are two special features of
this register bit that ensures proper sleep operation. First,
the write to set the register bit is blocked, if an interrupt is
about to be taken on that instruction boundary (immediately
after the write. Second, there is a hardware interlock to
ensure that once set, the sleep bit may not be cleared by an
incoming interrupt until the sleep circuit has finished per-
forming the sleep sequence and that the system wide power
down signal has been asserted. This prevents the sleep cir-
cuit from being interrupted in the middle of the process of
system power down, possibly leaving the system in an inde-
terminate state.
12.2
Application Description
The following are notes regarding sleep as it relates to firm-
ware and application issues.
1.
If an interrupt is pending, enabled, and scheduled to be
taken at the instruction boundary after the write to the
sleep bit, the system will not go to sleep. The instruction
will still execute, but it will not be able to set the SLEEP
bit in the CPU_SCR0 register. Instead, the interrupt will
be taken and the effect of the sleep instruction is
ignored.
2.
The global interrupt enable (CPU_F register) does not
need to be enabled to wake the system out of sleep
state. Individual interrupt enables, as set in the interrupt
mask registers, are sufficient. If the global interrupt
enable is not set, the CPU will not service the ISR asso-
ciated with that interrupt. However, the system will wake
up and continue executing instructions from the point at
which it went to sleep. In this case, the user must manu-
ally clear the pending interrupt or subsequently enable
the global interrupt enable bit and let the CPU take the
ISR. If a pending interrupt is not cleared, it will be contin-
uously asserted, and although the sleep bit may be writ-
ten and the sleep sequence executed, as soon as the
device enters Sleep mode, the sleep bit will be cleared
by the pending interrupt and Sleep mode will be exited.
3.
On wake up, the instruction immediately after the sleep
instruction will be executed before the interrupt service
routine (if enabled). The instruction after the sleep
instruction is pre-fetched before the system actually
goes to sleep. Therefore, when an interrupt occurs to
wake the system up, the pre-fetched instruction is exe-
cuted and then the interrupt service routine is executed.
(If the global interrupt enable is not set, instruction exe-
cution will just continue where it left off before sleep).
4.
If PLL mode is enabled, CPU frequency must be
reduced to 3 MHz before going to sleep. Since the PLL
will overshoot as it attempts to re-lock after wakeup, the
CPU frequency must be relatively low. It is recom-
mended to wait 10 ms after wakeup, before normal CPU
operating frequency may be restored.
5.
Analog power must be turned off by firmware, before
going to sleep. The system sleep state does not control
the analog array. There are individual power controls for
each analog block and global power controls in the refer-
ence block. These power controls must be manipulated
by firmware.
6.
If the global interrupt enable bit is disabled, it can be
safely enabled just before the instruction that writes the
sleep bit. It is usually undesirable to get an interrupt on
the instruction boundary, just before writing the sleep bit.
This means that on the return from interrupt, the sleep
command will be executed, possibly bypassing any firm-
ware preparations that need to be made in order to go to
sleep. To prevent this, disable interrupts before prepara-
tions are made. After sleep preparations, enable global
interrupts and write the sleep bit with the two consecu-
tive instructions as follows.
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| CY8C22213-24SIT | PSoC Mixed Signal Array |
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| CY8C24794-SPE | PSoCTM Mixed-Signal Array |
| CY8C24794-SPI | Explosion-Proof Limit Switches Series CX: Short Housing: Top Plunger; 1NC 1NO SPDT Snap Action; Number of internal basic switches BZ: 1; 0.75 in - 14NPT conduit |
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| CY8C22213-24SIT | 功能描述:IC MCU 2K FLASH 256B 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) |
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