參數(shù)資料
型號(hào)： CY8C22213-24SI
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO20
封裝： 0.300 INCH, MO-119, SOIC-20
文件頁(yè)數(shù)： 205/304頁(yè)
文件大?。?/td> 2956K
代理商： CY8C22213-24SI
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December 22, 2003
Document No. 38-12009 Rev. *D
205
CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
17.3.1
Timer Timing
Enable/Disable Operation.
When the block is disabled,
the clock is immediately gated low. All outputs are gated low,
including the interrupt output. All internal state is reset to its
configuration specific reset state, except for DR0, DR1, and
DR2, which are unaffected.
Terminal Count/Compare Operation.
In the clock cycle
following the count of 00h, the Terminal Count (TC) output is
asserted. It is one-half cycle or a full cycle depending on the
TC Pulse Width Mode, as set in the block Control register. If
this block is standalone, or if it is the least significant block in
a chain, the Carry Out (CO) signal is also asserted. If the
period is set to 00h, and the TC Pulse Width Mode is one-
half cycle, the output is the inversion of the input clock. The
Compare (CMP) output will be asserted in the cycle follow-
ing the compare true, and will be negated one cycle after
compare false.
Multi-Block Terminal Count/Compare Operation.
When
Timers are chained, the CO signal of a given block becomes
the CI of the next most significant block in the chain. In a
chained Timer, the CO output indicates that block and all
lower blocks are at 00h count. The CO is setup to the next
positive edge of the clock to enable the next higher block to
count once for every terminal count of all lower blocks.
The TCO of a given block becomes the TCI of the next least
significant block in the chain. The TCO output indicates that
that block and all higher blocks are at 00h count. The TCI/
TCO chaining signals provide a way for the lower blocks to
know when the upper blocks are at terminal count. Reload
occurs when all blocks are at terminal count, which can be
determined by CI, TCI and the block zero detect. Example
timing for a three block Timer is shown in
Figure 17-6
.
The compare circuit compares registers DR0 <= DR2.
(When Mode[1] = 1, the comparison is DR0 < DR2).
Each block has an internal compare condition (DR0 com-
pared to DR2), a chaining signal to the next block called
CMPO, and the chaining signal from the previous block
called CMPI In any given block of a Timer, the CMPO is
used to generate the auxiliary output (primary output in the
Counter) with a 1 cycle clock delay.
CMPO is generated from a combination of the internal com-
pare condition and the CMPI input by the following rules:
1.
For any given block, if DR0 < DR2, the CMPO condition
is unconditionally asserted.
2.
For any given block, if DR0 == DR2, CMPO is asserted
only if the CMPI input to that block is asserted.
3.
If the block is a start block, the effective CMPI depends
on the compare type. If it is DR0 <= DR2, the effective
CMPI input is '1'. If it is DR0 < DR2, the effective input is
'0'.
Capture Operation.
In the timer implementation, a rising
edge of the Data input or a CPU read of DR0 triggers a syn-
chronous capture event. The result of this is to generate a
latch enable to DR2 that loads the current count from DR0
into DR2. The latch enable signal is synchronized in such a
way that it is not closing near an edge on which the count is
changing.
A limitation is that capture will not work with the block clock
of 48 MHz. (A fundamental limitation to Timer capture opera-
tion is the fact the GPIO inputs are currently synchronized to
the 24 MHz system clock).
Figure 17-6. Multi-Block Timing
CLK
2
1
0
FF
FE
Count LSB
Example of Multi-block Timer Counting
MSB Period = k, ISB Period = m, LSB Period = n
Carry Out LSB
Count ISB
1
Carry Out ISB
0
2
1
0
n
n-1
0
m
0
Count MSB
Zero Detect LSB
Zero Detect ISB
k
Zero Detect MSB
Carry Out MSB
Multi-Block TC
Reload occurs
when all blocks
reach terminal
count.
相關(guān)PDF資料
PDF描述
CY8C22213-24SIT PSoC Mixed Signal Array
CY8C24794-SPAX PSoCTM Mixed-Signal Array
CY8C24794-SPE PSoCTM Mixed-Signal Array
CY8C24794-SPI Explosion-Proof Limit Switches Series CX: Short Housing: Top Plunger; 1NC 1NO SPDT Snap Action; Number of internal basic switches BZ: 1; 0.75 in - 14NPT conduit
CY8C24794-SPLFX Environmentally sealed limit switch with Leadwire termination, Rotary Roller Lever actuation, Double Pole Double Throw (DPDT) Circuitry, 5 A (Resistive) ampere rating at 28 Vdc, Military Part Number MS21320-1
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY8C22213-24SIT 功能描述:IC MCU 2K FLASH 256B 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類(lèi)型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán)
CY8C22345 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip
CY8C22345-12PVXE 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C22345-12PVXET 功能描述:可編程片上系統(tǒng) - PSoC M8C 8bit Flash 16KB RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
CY8C22345-24PVXA 功能描述:可編程片上系統(tǒng) - PSoC 24 I/O 16K FLASH 1K SRAM RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:67 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT
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