參數(shù)資料
型號(hào)： CY8C22213-24SI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： PSoC Mixed Signal Array
中文描述： MULTIFUNCTION PERIPHERAL, PDSO20
封裝： 0.300 INCH, MO-119, SOIC-20
文件頁(yè)數(shù)： 215/304頁(yè)
文件大?。?/td> 2956K
代理商： CY8C22213-24SI
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December 22, 2003
Document No. 38-12009 Rev. *D
215
CY8C22xxx Preliminary Data Sheet
17. Digital Blocks
17.3.8
Transmitter Timing
Enable/Disable Operation.
As soon as the block is config-
ured for Transmitter, and before enabling, the primary output
is set to idle at logic '1' the mark state. The output will remain
'1' until the block is enabled and a transmission is initiated.
The auxiliary output will also idle to '1', which is the idle state
of the associated SPI mode 3 clock.
When the Transmitter is enabled, the internal reset is
released on the divide by 8 clock generator circuit. On the
next positive edge of the selected input clock, this 3-bit up-
counter circuit, which generates the bit clock with the MSB,
starts counting up from 00h and is free-running thereafter.
When the block is disabled, the clock is immediately gated
low. All internal state is reset (including CR0 status) to its
configuration specific reset state, except for DR0, DR1, and
DR2, which are unaffected.
Transmit Operation.
Transmission is initiated with a write
to the TX Buffer register (DR1). The CPU write to this regis-
ter is required to have one-half bit clock setup time for the
data to be recognized at the next positive internal bit clock
edge. As shown in
Figure 17-23
, once the setup time is
met, there is one clock of latency until the data is loaded into
the shifter and the START bit is generated to the TXD (pri-
mary) output.
Figure 17-23. Typical Transmitter Timing
Figure 17-24
shows a detail of the Tx Buffer load timing. The
data bits are shifted out on each of the subsequent clocks.
Following the 8th bit, if parity is enabled, the parity bit is sent
to the output. Finally, the STOP bit is multiplexed into the
data stream. With one-half cycle setup to the next clock, if
new data is available from the TX Buffer register, the next
byte is loaded on the following clock edge and the process
is repeated. If no data is available, a mark (logic '1') is out-
put.
Figure 17-24. Tx Buffer Load Timing
The SCLK (auxiliary) output has an SPI mode 3 clock asso-
ciated with the data bits (for the mode 3 timing see
Figure 17-14
). During the mark (idle) and framing bits the
SCLK output is high.
Status Generation.
There are two status bits in the Trans-
mitter CR0 register: TX Reg Empty and TX Complete.
TX Reg Empty indicates that a new byte can be written to
the TX Buffer register. When the block is enabled, this status
bit is immediately asserted. This status bit is cleared when
the user writes a byte of data to the TX Buffer Register and
set when the data byte in the TX Buffer register is trans-
ferred into the shifter. If a transmission is not already in
progress, the assertion of this signal initiates one subject to
the timing.
The default interrupt in the Transmitter is tied to TX Reg
Empty. However, an initial interrupt is not generated when
the block is enabled. The user must write an initial byte to
the TX Buffer register. That byte must be transferred into the
shifter, before interrupts generated from the TX Reg Empty
status bit are enabled. This prevents an interrupt from occur-
ring immediately on block enable.
TX Complete is an optional interrupt and is generated when
all bits of data and framing bits have been sent. It is cleared
on a read of the CR0 register. This signal may be used to
determine when it is safe to disable the block after data
transmission is complete. In an interrupt driven Transmitter
INTERNAL CLOCK
TX REG EMPTY
START
TXD (F1)
D0
D4
D5
D6
D7
Free Running
clock is CLK
input divided
by 8.
User writes
first byte to the
TX Buffer
register.
Shifter is loaded
with the first byte.
User writes next
byte to the TX
Buffer register.
SCLK (F2)
Shifter is loaded with
the next byte.
STOP
PAR
TX Buffer write needs cycle
setup time to the internal clock.
1 cycle of latency before
START bit at the TXD output.
START
TXD
IOW
INTERNAL CLOCK
TXREGEMPTY
START
Write is valid on
rising edge of low.
A Tx Buffer write valid in this range will
result in a START bit 1 cycle, after the
subsequent rising edge of the clock.
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CY8C22213-24SIT 功能描述:IC MCU 2K FLASH 256B 20-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標(biāo)準(zhǔn)包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤
CY8C22345 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC Programmable System-on-Chip
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