參數(shù)資料
型號： CY7C68014A-56LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： D-SSK 110 KER
中文描述： 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220, QFN-56
文件頁數(shù)： 49/55頁
文件大?。?/td> 1958K
代理商： CY7C68014A-56LFXC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 49 of 55
9.16.3
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 9-19
diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of t
RDpwl
and minimum de-active
pulse width of t
RDpwh
. If SLCS is used then, SLCS must be
in asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition.)
The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of t
XFD
from the activating edge of SLRD. In
Figure 9-19
, data N is the first valid data read from the FIFO.
For data to appear on the data bus during the read cycle
(i.e. ,SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note:
In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
SLRD
FLAGS
SLOE
DATA
Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
RDpwh
t
RDpwl
t
OEon
t
XFD
t
XFLG
N
Data (X)
Driven
t
XFD
N+1
t
XFD
t
OEoff
N+3
N+2
t
OEoff
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
t
XFD
t
OEon
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
FAH
t
SFA
N
t=0
T=0
T=1
T=7
T=2
T=3
T=4
T=5
T=6
t=1
t=2
t=3
t=4
N
N
SLOE
SLRD
FIFO POINTER
N+3
FIFO DATA BUS
Not Driven
Driven: X
N
Not Driven
SLOE
N
N+2
N+3
Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
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參數(shù)描述
CY7C68014A-56LTXC 功能描述:8位微控制器 -MCU USB HS Controller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
CY7C68014A-56PVXC 功能描述:8位微控制器 -MCU EZ USB FX2LP Battery Apps LO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
CY7C68014A-BAXC 制造商:Cypress Semiconductor 功能描述:MCU 8BIT CISC ROMLESS 3.3V 100TQFP - Trays
CY7C68015A-56LFXC 功能描述:8位微控制器 -MCU EZ USB FX2LP LO PWR Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
CY7C68015A-56LTXC 功能描述:USB 接口集成電路 USB HS Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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