參數(shù)資料
型號： CY7C68014A-56LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： D-SSK 110 KER
中文描述： 8-BIT, EEPROM, 48 MHz, MICROCONTROLLER, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220, QFN-56
文件頁數(shù)： 26/55頁
文件大?。?/td> 1958K
代理商： CY7C68014A-56LFXC
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Document #: 38-08032 Rev. *G
Page 26 of 55
70
55
37
30
CTL1 or
FLAGB
O/Z
H
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL1
is a GPIF control output.
FLAGB
is a programmable slave-FIFO output status
flag signal.
Defaults to FULL for the FIFO selected by the
FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL2
is a GPIF control output.
FLAGC
is a programmable slave-FIFO output status
flag signal.
Defaults to EMPTY for the FIFO selected by the
FIFOADR[1:0] pins.
CTL3
is a GPIF control output.
CTL4
is a GPIF control output.
CTL5
is a GPIF control output.
Interface Clock, used for synchronously clocking data
into or out of the slave FIFOs. IFCLK also serves as a
timing reference for all slave FIFO control signals and
GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz
by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by
setting the bit IFCONFIG.4 =1.
-----------------------------------------------------------------------
Multiplexed pin whose function is selected by the
PORTECFG.0 bit.
PE0
is a bidirectional I/O port pin.
T0OUT
is an active-HIGH signal from 8051 Timer-
counter0. T0OUT outputs a high level for one CLKOUT
clock cycle when Timer0 overflows. If Timer0 is
operated in Mode 3 (two separate timer/counters),
T0OUT is active when the low byte timer/counter
overflows.
INT4
is the 8051 INT4 interrupt request input signal. The
INT4 pin is edge-sensitive, active HIGH.
INT5#
is the 8051 INT5 interrupt request input signal.
The INT5 pin is edge-sensitive, active LOW.
T2
is the active-HIGH T2 input signal to 8051 Timer2,
which provides the input to Timer2 when C/T2 = 1.
When C/T2 = 0, Timer2 does not use this pin.
T1
is the active-HIGH T1 signal for 8051 Timer1, which
provides the input to Timer1 when C/T1 is 1. When C/T1
is 0, Timer1 does not use this bit.
T0
is the active-HIGH T0 signal for 8051 Timer0, which
provides the input to Timer0 when C/T0 is 1. When C/T0
is 0, Timer0 does not use this bit.
RXD1
is an active-HIGH input signal for 8051 UART1,
which provides data to the UART in all modes.
TXD1
is an active-HIGH output pin from 8051 UART1,
which provides the output clock in sync mode, and the
output data in async mode.
71
56
38
31
CTL2 or
FLAGC
O/Z
H
66
67
98
32
51
52
76
26
CTL3
CTL4
CTL5
IFCLK on
CY7C68013A
O/Z
Output
Output
I/O/Z
H
H
H
Z
20
13
------------------
PE0 or T0OUT
on
CY7C68015A
-----------
I/O/Z
----------
I
(PE0)
28
22
INT4
Input
N/A
106
84
INT5#
Input
N/A
31
25
T2
Input
N/A
30
24
T1
Input
N/A
29
23
T0
Input
N/A
53
43
RXD1
Input
N/A
52
42
TXD1
Output
H
Table 4-1. FX2LP Pin Descriptions
(continued)
[10]
128
TQFP
100
TQFP
56
SSOP
56
QFN
Name
Type
Default
Description
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CY7C68014A-56LTXC 功能描述:8位微控制器 -MCU USB HS Controller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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CY7C68014A-BAXC 制造商:Cypress Semiconductor 功能描述:MCU 8BIT CISC ROMLESS 3.3V 100TQFP - Trays
CY7C68015A-56LFXC 功能描述:8位微控制器 -MCU EZ USB FX2LP LO PWR Extra GPIO COM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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