
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 61 of 74
25.0
Absolute Maximum Ratings
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with Power Applied ..... –0°C to +70°C
Supply Voltage on V
CC
Relative to V
SS
..........–0.5V to +7.0V
DC Input Voltage................................ –0.5V to + V
CC
+ 0.5V
DC Voltage Applied to Outputs in
High-Z State ...................................... –0.5V to + V
CC
+ 0.5V
Maximum Total Sink Output Current into Port 0
and 1 and Pins.............................................................70 mA
Maximum Total Source Output Current into GPIO Pins30 mA
Maximum On-chip Power Dissipation
on any GPIO Pin.........................................................50 mW
Power Dissipation ....................................................300 mW
Static Discharge Voltage .............................................2200V
Latch-up Current ...................................................... 200 mA
26.0
DC Characteristics
Parameter
V
CC1
V
CC2
V
CC3
V
CC4
Description
General
Conditions
Min.
4.0
4.35
4.35
4.75
Typical
Max.
5.5
5.25
5.25
5.5
Unit
V
V
V
V
Operating Voltage
Operating Voltage
Operating Voltage
Operating Voltage
No USB activity, CPU speed < 12 MHz
USB activity, CPU speed < 12 MHz
Flash programming
No USB activity, CPU speed < 24
MHz
Flash Programming
V
= 5.25V, no GPIO loading,
24 MHz
V
CC
= 5.0V, no GPIO loading, 6 MHz
Internal and External Oscillators,
Bandgap, Flash, CPU Clock, Timer
Clock, USB Clock all disabled
T
FP
I
CC1
Operating Temp
V
CC
Operating Supply Current
0
70
40
°C
mA
I
CC2
I
SB1
V
CC
Operating Supply Current
Standby Current
10
mA
μ
A
10
Low-voltage Detect
V
LVD
Low-voltage detect Trip Voltage
(8 programmable trip points)
3.3V Regulator
I
VREG
Max Regulator Output Current
I
KA
Keep Alive Current
2.681
4.872
V
4.35V < V
CC
< 5.5V
When regulator is disabled with
“keep alive” enable
Keep Alive bit set in VREGCR
V
> 4.35V, 0 < temp < 40°C,
25 mA < I
< 125 mA (3.3V ± 8%)
T = 0 to 70C
V
> 4.35V, 0 < temp < 40°C,
1 mA < I
< 25 mA (3.3V ± 4%)
T = 0 to 40C
125
20
mA
μ
A
V
KA
V
REG1
Keep Alive Voltage
V
REG
Output Voltage
2.35
3.0
3.8
3.6
V
V
V
REG2
V
REG
Output Voltage
3.15
3.45
V
C
LOAD
LN
REG
LD
REG
USB Interface
V
ON
V
OFF
V
DI
V
CM
Capacitive load on Vreg pin
Line Regulation
Load Regulation
1
2
1
μ
F
%/V
%/mA
0.04
Static Output High
Static Output Low
Differential Input Sensitivity
Differential Input Common Mode
Range
Single Ended Receiver Threshold
Transceiver Capacitance
Hi-Z State Data Line Leakage
15K ± 5% Ohm to V
SS
R
UP
is enabled
2.8
3.6
0.3
V
V
V
V
0.2
0.8
2.5
V
SE
C
IN
I
IO
0.8
2
20
10
V
pF
μ
A
0V < V
IN
< 3.3V
–10