參數(shù)資料
型號(hào)： CY7C63833
廠商： Cypress Semiconductor Corp.
英文描述： enCoRe II Low-Speed USB Peripheral Controller(enCoRe II低速USB外設(shè)控制器)
中文描述： enCoRe II還低速USB外設(shè)控制器（enCoRe II還低速的USB外設(shè)控制器）
文件頁(yè)數(shù)： 55/74頁(yè)
文件大小： 1441K
代理商： CY7C63833
CY7C63310
CY7C638xx
Document 38-08035 Rev. *I
Page 55 of 74
21.4
Endpoint 1 and 2 Mode
Table 21-4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Stall
Reserved
NAK Int Enable
ACK’d
Transaction
Mode[3:0]
Read/Write
R/W
R/W
R/W
R/C (Note 4)
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit 7:
Stall
When this bit is set the SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if
the mode bits are set to ACK-IN. This bit must be clear for all other modes
Bit 6:
Reserved
Bit 5:
NAK Int Enable
This bit when set causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike enCoRe,
enCoRe II family members do not generate an endpoint interrupt under these conditions unless this bit is set
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
Bit 4:
ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an
ACK packet.
This bit is cleared by any writes to the register
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Bit [3:0]:
Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how the
USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to the endpoint.
Note:
When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the EP1MODE
registers respectively (if both writes occur in the same clock cycle). This is because the design employs only one common ‘update’
signal for both EP1MODE and EP2MODE registers. Thus, when SIE writes to say EP1MODE register, the update signal is set and
this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have higher priority than firmware
writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware must read the EP1/2MODE regis-
ters immediately following a firmware write and rewrite if the value read is incorrect.
Table 21-5. Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Endpoint 0 Data Buffer [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
Table 21-6. Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Endpoint 1 Data Buffer [7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F
Table 21-7. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Endpoint 2 Data Buffer [7:0]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C638334-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LFXC 制造商:Cypress Semiconductor 功能描述:
CY7C638335-LTXC 制造商:Cypress Semiconductor 功能描述:
CY7C63833-LFXC 功能描述:USB 接口集成電路 8K Flash 256 byte RAM COM RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
CY7C63833-LTXC 功能描述:USB 接口集成電路 USB Peripheral Cntrl 8K/256 32-QFN RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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