參數(shù)資料
型號: CY7C4425
廠商: Cypress Semiconductor Corp.
英文描述: 64 x 18 Synchronous FIFOs(64 x 18 同步 先進(jìn)先出)
中文描述: 64 × 18(64 × 18同步先進(jìn)先出同步FIFO的)
文件頁數(shù): 5/25頁
文件大?。?/td> 398K
代理商: CY7C4425
CY7C4425/4205/4215
CY7C4225/4235/4245
5
Capacitance
[7]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
5
7
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
AC Test Loads and Waveforms
[8, 9]
3.0V
5V
OUTPUT
R11.1K
R2
680
C
L
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 3 ns
< 3 ns
OUTPUT
1.91V
Equivalentto:
TEVENIN
EQUIVALENT
410
42X5–4
ALL INPUT PULSES
42X5–5
Switching Characteristics
Over the Operating Range
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSR
t
RSF
t
PRT
t
RTR
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
Notes:
7.
Tested initially and after any design or process changes that may affect these parameters.
8.
C
L
= 30 pF for all AC parameters except for t
OHZ
.
9.
C
= 5 pF for t
.
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
Description
7C42X5-10
Min.
7C42X5-15
Min.
7C42X5-25
Min.
7C42X5-35
Min.
Max.
100
8
Max.
66.7
10
Max.
40
15
Max.
28.6
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[10]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z
[11]
Output Enable to Output Valid
Output Enable to Output in High Z
[11]
Write Clock to Full Flag
Read Clock to Empty Flag
2
2
15
6
6
4
1
4
1
15
10
2
25
10
10
6
1
6
1
25
15
2
35
14
14
7
2
7
2
35
20
10
4.5
4.5
3
0.5
3
0.5
10
8
10
15
25
35
12
12
0
3
3
15
15
0
3
3
25
25
0
3
3
35
35
0
3
3
7
7
8
8
8
8
12
12
15
15
15
15
20
20
10
10
相關(guān)PDF資料
PDF描述
CY7C4211 512 x 9 Synchronous FIFOs(512x9同步先進(jìn)先出(FIFO))
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CY7C4221 1K x 9 Synchronous FIFOs(1Kx9同步先進(jìn)先出(FIFO))
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