參數(shù)資料
型號(hào)： CY7C43686
廠商： Cypress Semiconductor Corp.
英文描述： 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出)
中文描述： 16K的x36/x18x2三總線的FIFO（16K的x36/x18x2三路總線先進(jìn)先出）
文件頁(yè)數(shù)： 8/40頁(yè)
文件大?。?/td> 577K
代理商： CY7C43686
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
8
PRELIMINARY
Switching Characteristics
Over the Operating Range
Parameter
Description
7C43626/
36/46/66/86
-7
7C43626/
36/46/66/86
-10
7C43626/
36/46/66/86
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
f
S
t
CLK
t
CLKH
t
CLKL
Clock Frequency, CLKA,CLKB, or CLKC
133
100
67
MHz
Clock Cycle Time, CLKA,CLKB, or CLKC
7.5
10
15
ns
Pulse Duration, CLKA,CLKB, or CLKC HIGH
3.5
4
6
ns
Pulse Duration, CLKA,CLKB, or CLKC LOW
Set-Up Time, A
0
–
35
before CLKA
↑
B
0
–
17
before
CLKB
↑,
and C
0
–
17
before CLKC
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
; RENB and MBB before CLKB
↑
and WENC
and MBC before CLKC
↑
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW
before CLKA
↑
or CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before MRS1 and MRS2
HIGH
3.5
4
6
ns
t
DS
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
5
7
7.5
ns
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
5
7
7.5
ns
Set-Up Time, SPM before MRS1 and MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
↑
Set-Up Time, FS1/SEN before CLKA
↑
Set-Up Time, FWFT before CLKA
↑
Hold Time, A
0
–
35
before CLKA
↑
B
0
–
17
before CLKB
↑,
and C
0
–
17
before CLKC
↑
Hold Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
RENB and MBB before CLKB
↑
and WENC
and MBC before CLKC
↑
Hold Time, MRS1, MRS2, PRS1, or PRS2 LOW after
CLKA
↑
or CLKB
↑
[7]
Hold Time, FS0 and FS1 after MRS1 and MRS2
HIGH
5
7
7.5
ns
3
4
5
ns
3
4
5
ns
0
0
0
ns
t
DH
0
0
0
ns
t
ENH
0
0
0
ns
t
RSTH
1
2
4
ns
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
1
1
2
ns
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
1
1
2
ns
Hold Time, SPM after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA
↑
Hold Time, FS1/SEN after CLKA
↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2
HIGH
Skew Time between CLKA
↑
and CLKB
↑
for EFA/
ORA, EFB/ORB, FFA/IRA, and FFC/IRC
Skew Time between CLKA
↑
and CLKB
↑
for AEA,
AEB, AFA, AFC
Access Time, CLKA
↑
to A
0
–
35
and CLKB
↑
to B
0
–
17
Propagation Delay Time, CLKA
↑
to FFA/IRA and
CLKB
↑
to FFC/IRC
1
1
2
ns
0
0
0
ns
0
0
0
ns
t
SPH
0
1
2
ns
t
SKEW1[8]
5
5
7.5
ns
t
SKEW2[8]
t
A
7
8
12
ns
1
6
1
8
3
10
ns
t
WFF
Notes:
7.
8.
1
6
1
8
2
8
ns
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
相關(guān)PDF資料
PDF描述
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出)
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出)
CY7C43663AV 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43683AV 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配)
CY7C43664AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43686-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
CY7C439-40DMB 制造商:Cypress Semiconductor 功能描述:
CY7C441-14JC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC
CY7C441-30JC 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC
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