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參數資料
| 型號： | CY7C43686 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出) |
| 中文描述： | 16K的x36/x18x2三總線的FIFO（16K的x36/x18x2三路總線先進先出） |
| 文件頁數： | 7/40頁 |
| 文件大小： | 577K |
| 代理商： | CY7C43686 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
7
PRELIMINARY
Notes:
4.
Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
All inputs = V
–
0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
Tested initially and after any design or process changes that may affect these parameters.
5.
6.
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
V
CC
= 4.5V., I
OH
=
4.0 mA
V
CC
= 4.5V., I
OL
= 8.0 mA
7C43626/36/46/66/86
Unit
Min.
Max.
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZL
I
OZH
I
CC1[4]
Output HIGH Voltage
2.4
V
Output LOW Voltage
0.5
V
Input HIGH Voltage
2.0
0.5
10
10
V
CC
0.8
V
Input LOW Voltage
V
μ
A
μ
A
Input Leakage Current
V
CC
= Max.
V
SS
< V
O
< V
CC
+10
Output OFF, High Z
Current
+10
Active Power Supply
Current
Com
’
l
100
mA
Ind
100
mA
I
SB[5]
Average Standby
Current
Com
’
l
10
mA
Ind
10
mA
Capacitance
[6]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
4
8
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms (-7)
3.0V
5V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=1.1 K
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0=50
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相關代理商/技術參數 |
參數描述 |
|---|---|
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| CY7C439-40DMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C441-14JC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Width Uni-Dir 512 x 9 32-Pin PLCC |
| CY7C441-30JC | 制造商:Cypress Semiconductor 功能描述:FIFO, 512 x 9, Synchronous, 32 Pin, Plastic, PLCC |
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