參數(shù)資料
型號(hào)： CY7C43683AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配)
中文描述： 3.3 16K的x36單向同步FIFO瓦特/總線匹配（3.3 16K的x36單向同步先進(jìn)先出帶總線匹配）
文件頁(yè)數(shù)： 7/28頁(yè)
文件大小： 420K
代理商： CY7C43683AV
CY7C43643AV
CY7C43663AV/CY7C43683AV
7
PRELIMINARY
AC Test Loads and Waveforms (-10, -15)
AC Test Loads and Waveforms (-7)
Switching Characteristics
Over the Operating Range
Parameter
Description
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Clock Frequency, CLKA or CLKB
133
100
67
MHz
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A
0
–
35
before CLKA
↑
and B
0
–
35
before
CLKB
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
; CSB, W/RB, ENB, and MBB before CLKB
↑
Set-Up Time, MRS1/MRS2 or PRS LOW before
CLKA
↑
or CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
5
7
7.5
ns
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH
5
7
7.5
ns
Set-Up Time, SPM before MRS1/MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
↑
Set-Up Time, FS1/SEN before CLKA
↑
Set-Up Time, FWFT before CLKA
↑
Hold Time, A
0
–
35
after CLKA
↑
and B
0
–
35
after
CLKB
↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA
↑
;
CSB, W/RB, ENB, and MBB after CLKB
↑
5
7
7.5
ns
3
4
5
ns
3
4
5
ns
0
0
0
ns
0
0
0
ns
t
ENH
1
2
0
ns
Note:
7.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=330
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
VCC/2
Z0=50
相關(guān)PDF資料
PDF描述
CY7C43664AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43644AV 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43684AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
CY7C43666AV 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出)
CY7C43686AV 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C43683AV-15AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk
CY7C43684-10AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43684AV-10AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk
CY7C43686-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43686AV-7AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP
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