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參數(shù)資料
| 型號(hào)： | CY7C43683AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 3.3 16K的x36單向同步FIFO瓦特/總線匹配（3.3 16K的x36單向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 420K |
| 代理商： | CY7C43683AV |
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CY7C43643AV
CY7C43663AV/CY7C43683AV
21
PRELIMINARY
To program the X and Y registers from Port A, perform a Mas-
ter Reset on both FIFOs simultaneously with SPM HIGH and
FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1, MRS2. After this reset is complete, the first two writes
to the FIFO do not store data in RAM but load the offset regis-
ters in the order Y and X. The Port A data inputs used by the
offset registers are (A
0
–
9
), (A
0
–
11
), or (A
0
–
13
), for the
CY7C436X3AV, respectively. The highest numbered input is
used as the most significant bit of the binary number in each
case. Valid programming values for the registers range from 1
to 1012 for the CY7C43643AV; 1 to 4092 for the
CY7C43663AV; 1 to 16380 for the CY7C43683AV. Before pro-
gramming the offset registers, FF/IR is set HIGH. FIFOs begin
normal operation after programming is complete.
To program the X and Y registers serially, initiate a Master
Reset with SPM LOW, FS0/SD LOW, and FS1/SEN HIGH dur-
ing the LOW-to-HIGH transition of MRS1, MRS2. After this
reset is complete, the X and Y register values are loaded bit-
wise through the FS0/SD input on each LOW-to-HIGH transi-
tion of CLKA that the FS1/SEN input is LOW. Twenty, twenty-
four, or twenty-eight bit writes are needed to complete the pro-
gramming for the CY7C436X3AV, respectively. The two regis-
ters are written in the order Y then finally X. The first-bit write
stores the most significant bit of the Y register and the last-bit
write stores the least significant bit of the X register. Each reg-
ister value can be programmed from 1 to 1020
(CY7C43643AV), 1 to 4092 (CY7C43663AV), or 1 to 16380
(CY7C43683AV).
When the option to program the offset registers serially is cho-
sen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the LOW-
to-HIGH transition of CLKA after the last bit is loaded to allow
normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A
0
–
35
) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A
0
–
35
lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A
0
–
35
lines are active outputs
when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A
0
–
35
inputs on a LOW-
to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see
Table 2
).
FIFO writes on Port A are independent of any concurrent Port
B operation.
The Port B control signals are identical to those of Port A with
the exception that the Port B Write/Read select (W/RB) is the
inverse of the Port A Write/Read select (W/RA). The state of
the Port B data (B
0
–
35
) lines is controlled by the Port B Chip
Select (CSB) and Port B Write/Read select (W/RB). The B
0
–
35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B
0
–
35
lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B
0
–
35
outputs by a LOW-to-
HIGH transition of CLKB when CSB is LOW, W/RB is HIGH,
ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see
Table 3
).
FIFO reads and writes on Port B are independent of any con-
current Port A operation.
The set-up and hold time constraints to the port clocks for the
port Chip Selects and Write/Read Selects are only for enabling
write and read operations and are not related to high-imped-
ance control of the data outputs. If a port enable is LOW during
a clock cycle, the port
’
s Chip Select and Write/Read Select
may change states during the set-up and hold time window of
the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW, the next word written is automatically sent to
the FIFO
’
s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
siding in the FIFO
’
s memory array is clocked to the output reg-
ister only when a read is selected using the port
’
s Chip Select,
Write/Read Select, Enable, and Mailbox Select.
When operating the FIFO in CY Standard Mode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO
’
s memory array is clocked to the output register only
when a read is selected using the port
’
s Chip Select, Write/
Read Select, Enable, and Mailbox Select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two flip-flop stages. This is done to improve flag-signal reliabil-
ity by reducing the probability of the metastable events when
CLKA and CLKB operate asynchronously to one another. EF/
OR and AE are synchronized to CLKA. FF/IR and AF are syn-
chronized to CLKB.
Table 4
shows the relationship of each port
flag to the FIFO.
Empty/Output Ready Flags (EF/OR)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready (OR) function is selected. When the Output Ready flag
is HIGH, new data is present in the FIFO output register. When
the Output Ready flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO
’
s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word is present
in the FIFO output register and attempted FIFO reads are ig-
nored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is increment-
ed each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from the time a word is written to a FIFO, it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to the FIFO output register and three cy-
cles have not elapsed since the time the word was written. The
Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs, si-
multaneously forcing the Output Ready flag HIGH and shifting
the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty flag
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參數(shù)描述 |
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| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
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| CY7C43686AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Triple Depth/Width Tri-Bus 16K x 36/16K x 18 x 2 128-Pin TQFP |
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