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參數(shù)資料
| 型號(hào)： | CY7C43666 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出) |
| 中文描述： | 4K的x36/x18x2三總線的FIFO（4K的x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 5/40頁 |
| 文件大小： | 577K |
| 代理商： | CY7C43666 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
5
PRELIMINARY
FFA/IRA
Port A Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard Mode, the FFC function is selected. FFC
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function
is selected. IRC indicates whether or not there is space available for writing to the FIFO2
memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKB.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values (8, 16, or 64), parallel load from Port A,
and serial load. When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When
FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X
and Y registers. The number of bit writes required to program the offset registers is 32
for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the
CY7C43666, and 56 for the CY7C43686. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
FS0/SD
Flag Offset
Select 0/Serial
Data
I
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When the A
0
35
outputs are active, a HIGH level on MBA selects data from the Mail2
register for output and a LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B
0
17
outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
MBC
Port C Mailbox
Select
I
A HIGH level on MBC chooses a mailbox register for a Port C read or write operation.
When the C
0
17
outputs are active, a HIGH level on MBC selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
FIFO1 Master
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2
FIFO2 Master
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
PRS1
FIFO1 Partial
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
PRS2
FIFO2 Partial
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
Pin Definitions
(continued)
Signal Name
Description
I/O
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43682AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43663AV | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
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