參數(shù)資料
型號: CY7C43666
廠商: Cypress Semiconductor Corp.
英文描述: 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出)
中文描述: 4K的x36/x18x2三總線的FIFO(4K的x36/x18x2三路總線先進先出)
文件頁數(shù): 24/40頁
文件大?。?/td> 577K
代理商: CY7C43666
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
24
PRELIMINARY
Notes:
36. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively.
37. t
is the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKC edge is less than t
SKEW1
, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[37]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in
FIFO2 Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKC
FFC/IRC
MBC
WENC
C
0
17
IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
[36]
相關(guān)PDF資料
PDF描述
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出)
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出)
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進先出)
CY7C43663AV 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進先出帶總線匹配)
CY7C43683AV 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進先出帶總線匹配)
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