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參數(shù)資料
| 型號： | CY7C43666 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出) |
| 中文描述： | 4K的x36/x18x2三總線的FIFO（4K的x36/x18x2三路總線先進(jìn)先出） |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CY7C43666 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
27
PRELIMINARY
Notes:
46. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 Read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from
the FIFO.
47. D = Maximum FIFO Depth = 256 for the CY7C43626, 512 for the CY7C43636, 1K for the CY7C43646, 4K for the CY7C43666, and 16K for the CY7C43686.
48. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
49. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
, then AFA may transition HIGH one CLKB cycle later than shown.
50. If Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
51. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than t
SKEW2
, then AFC may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y1+1)] Words in FIFO1
(D
–
Y1)Words in FIFO1
t
SKEW2[49]
CLKA
ENA
AFA
CLKB
RENB
[46, 47, 48]
t
PAF
t
ENH
t
ENS
t
PAF
t
ENS
t
ENH
[D
–
(Y2+1)] Words in FIFO2
(D
–
Y2)Words in FIFO2
t
SKEW2[51]
CLKC
WENC
AFC
CLKA
ENA
Timing for AFC when FIFO2 is Almost Full (CY Standard and FWFT Modes)
[43, 47, 50]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43682AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進(jìn)先出) |
| CY7C43663AV | 3.3V 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 單向同步先進(jìn)先出帶總線匹配) |
| CY7C43683AV | 3.3V 16K x36 Unidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 單向同步先進(jìn)先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43684AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk |
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