參數(shù)資料
型號： CY7C43664AV
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進先出帶總線匹配)
中文描述： 3.3 4K的x36 x2雙向同步FIFO瓦特/總線匹配（3.3 4K的x36 x2雙向同步先進先出帶總線匹配）
文件頁數(shù)： 4/38頁
文件大?。?/td> 581K
代理商： CY7C43664AV
CY7C43644AV
CY7C43664AV/CY7C43684AV
4
PRELIMINARY
Pin Definitions
Signal Name
A
0
–
35
AEA
Description
Port A Data
Port A Almost
Empty Flag
I/O
I/O
O
Function
36-bit bidirectional data port for side A.
Programmable Almost Empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2.
Programmable Almost Empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1.
Programmable Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
Programmable Almost Full flag synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
36-bit bidirectional data port for side B.
This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data
flow). A LOW on BE will select Little Endian operation. In this case, the least significant
byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port
B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH
on FWFT selects CY Standard mode, a LOW selects First-Word Fall-Through mode.
Once the timing mode has been selected, the level on FWFT must be static throughout
device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0
–
35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0
–
35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0
–
35
outputs, avail-
able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual-function pin. In the CY Standard mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
0
–
35
outputs, avail-
able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
This is a dual-function pin. In the CY Standard mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
AEB
Port B Almost
Empty Flag
O
AFA
Port A Almost
Full Flag
O
AFB
Port B Almost
Full Flag
O
B
0
–
35
BE/FWFT
Port B Data
Big Endian/
First-Word Fall-
Through Select
I/O
I
BM
Bus Match
Select (Port A)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
I
CSB
I
EFA/ORA
O
EFB/ORB
Port B Empty/
Output Ready
Flag
O
ENA
Port A Enable
I
ENB
Port B Enable
I
FFA/IRA
Port A Full/Input
Ready Flag
O
相關PDF資料
PDF描述
CY7C43644AV 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進先出帶總線匹配)
CY7C43684AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進先出帶總線匹配)
CY7C43666AV 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進先出)
CY7C43686AV 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進先出)
CY7C453 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標記的2Kx9可級聯(lián)定時的先進先出)
相關代理商/技術參數(shù)
參數(shù)描述
CY7C43682-15AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43683-10AI 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43683AV-15AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk
CY7C43684-10AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C43684AV-10AC 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 16K x 36 x 2 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V BIDIR SYNC FIFO W/ BUS MATCHING 16KX32X2 - Bulk
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