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參數(shù)資料
| 型號： | CY7C43664AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 4K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 3.3 4K的x36 x2雙向同步FIFO瓦特/總線匹配（3.3 4K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數(shù)： | 27/38頁 |
| 文件大小： | 581K |
| 代理商： | CY7C43664AV |
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CY7C43644AV
CY7C43664AV/CY7C43684AV
27
PRELIMINARY
Notes:
49. If Port B is configured for word size, data can be written to the Mail2 register using B
(B
are
“
Don
’
t Care
”
inputs). In this first case A
0
will have
valid data (A
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B
0
–
8
(B
9
–
35
are
“
Don
’
t Care
”
inputs). In this second case, A
will have valid data (A
9
–
35
will be indeterminate).
50. Retransmit is performed in the same manner for FIFO2.
51. Clocks are free running in this case.
52. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
53. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B
0
–
35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0-35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[49]
FIFO1 Retransmit Timing
ENB
RT1
t
PRT
t
RTR
EFB/FFA
[50, 51, 52, 53]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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