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參數(shù)資料
| 型號： | CY7C43664 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 4K的x36 x2雙向同步FIFO瓦特/總線匹配（4K的x36 x2雙向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 5/37頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43664 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
5
PRELIMINARY
FFB/IRB
Port B Full/Input
Ready Flag
O
This is a dual-function pin. In the CY Standard mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag
offset programming method. Three offset register programming methods are available:
automatically load one of three preset values (8, 16, or 64), parallel load from Port A,
and serial load. When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When
FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X
and Y registers. The number of bit writes required to program the offset registers is 32
for the CY7C43624, 36 for the CY7C43634, 40 for the CY7C43644, 48 for the
CY7C43664, and 56 for the CY7C43684. The first bit write stores the Y-register MSB
and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When the A
0
–
35
outputs are active, a HIGH level on MBA selects data from the Mail2
register for output and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B
0
–
35
outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets for FIFO1. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
A LOW strobe on this pin will retransmit data on FIFO1 from the location of the write
pointer at the last Partial or Master reset.
A LOW strobe on this pin will retransmit data on FIFO2 from the location of the write
pointer at the last Partial or Master reset.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
FS1/SEN
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
I
FS0/SD
I
MBA
Port A Mailbox
Select
I
MBB
Port B Mailbox
Select
I
MBF1
Mail1 Register
Flag
O
MBF2
Mail2 Register
Flag
O
MRS1
FIFO1 Master
Reset
I
MRS2
FIFO2 Master
Reset
I
PRS1
FIFO1 Partial
Reset
I
PRS2
FIFO2 Partial
Reset
I
RT1
Retransmit
FIFO1
Retransmit
FIFO2
Bus Size Select
I
RT2
I
SIZE
I
Pin Definitions
(continued)
Signal Name
Description
I/O
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43684 | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43636 | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出) |
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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