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參數資料
| 型號： | CY7C43664 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進先出帶總線匹配) |
| 中文描述： | 4K的x36 x2雙向同步FIFO瓦特/總線匹配（4K的x36 x2雙向同步先進先出帶總線匹配） |
| 文件頁數： | 24/37頁 |
| 文件大小： | 581K |
| 代理商： | CY7C43664 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
24
PRELIMINARY
Notes:
37. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
38. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
39. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition HIGH one CLKB cycle later than shown.
40. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
41. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
42. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[39]
t
ENS
t
ENH
X1 Word in FIFO1
(X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
ENB
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[37, 38]
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[42]
t
ENS
t
ENH
X2 Word in FIFO2
(X2+1)Words in FIFO2
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[40, 41]
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C43684 | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進先出帶總線匹配) |
| CY7C43636 | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進先出) |
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
| CY7C43684-10AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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