參數(shù)資料
型號: CY7C43626
廠商: Cypress Semiconductor Corp.
英文描述: 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出)
中文描述: 256 x36/x18x2三總線的FIFO(256 x36/x18x2三路總線先進(jìn)先出)
文件頁數(shù): 25/40頁
文件大?。?/td> 577K
代理商: CY7C43626
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
25
PRELIMINARY
Notes:
38. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively.
39. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFC to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKC edge is less than t
SKEW1
, then the transition of FFC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[39]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO2
Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKC
FFC/IRC
MBC
ENB
C
0
17
FFC Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
[38]
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PDF描述
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進(jìn)先出)
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