參數資料
型號: CY7C43626
廠商: Cypress Semiconductor Corp.
英文描述: 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出)
中文描述: 256 x36/x18x2三總線的FIFO(256 x36/x18x2三路總線先進先出)
文件頁數: 21/40頁
文件大小: 577K
代理商: CY7C43626
CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
21
PRELIMINARY
Notes:
31. If Port C size is word or byte, t
is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
32. t
is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than t
SKEW1
, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms
(continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
t
DH
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[32]
CLKC
MBC
WENC
FFC/IRC
C
0
17
CLKA
EFA/IRA
CSA
W/RA
MBA
ENA
A
0
35
[31]
相關PDF資料
PDF描述
CY7C43646 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出)
CY7C43666 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出)
CY7C43686 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出)
CY7C43662AV 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出)
CY7C43682AV 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進先出)
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