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參數(shù)資料
| 型號： | CY7C43622 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x36 x2 Bidirectional Synchronous FIFO(256 x36 x2 雙向同步先進先出) |
| 中文描述： | 256 x36 x2雙向同步FIFO（256 x36 x2雙向同步先進先出） |
| 文件頁數(shù)： | 5/31頁 |
| 文件大小： | 463K |
| 代理商： | CY7C43622 |
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CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
5
PRELIMINARY
FS1
Flag Offset
Select 1
I
The LOW-to-HIGH transition of a FIFO
’
s reset input latches the values of FS0 and FS1.
If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
values (8, 16, or 64) is selected as the offset for the FIFO
’
s Almost Full and Almost
Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW
when RST1 and RST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for
both FIFOs.
FS0
Flag Offset
Select 0
I
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When the A
0
–
35
outputs are active, a HIGH level on MBA selects data from the Mail2
register for output and a LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B
0
–
35
outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
RST1
FIFO1 Master
Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on RST1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH tran-
sitions of CLKB must occur while RST1 is LOW.
RST2
FIFO2 Master
Reset
I
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on RST2 selects
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is
LOW.
W/RA
Port A Write/
Read Select
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-to-HIGH transition of CLKA. The A
0
–
35
outputs are in the HIGH impedance state
when W/RA is HIGH.
W/RB
Port B Write/
Read Select
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIGH transition of CLKB. The B
0
–
35
outputs are in the HIGH impedance state
when W/RB is LOW.
Pin Definitions
(continued)
Signal Name
Description
I/O
Function
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C43682 | 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進先出) |
| CY7C43633 | 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進先出帶總線匹配) |
| CY7C43623 | 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進先出帶總線匹配) |
| CY7C43643 | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配) |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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