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參數(shù)資料
| 型號： | CY7C43622 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x36 x2 Bidirectional Synchronous FIFO(256 x36 x2 雙向同步先進先出) |
| 中文描述： | 256 x36 x2雙向同步FIFO（256 x36 x2雙向同步先進先出） |
| 文件頁數(shù)： | 21/31頁 |
| 文件大小： | 463K |
| 代理商： | CY7C43622 |
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CY7C43622
CY7C43632/CY7C43642
CY7C43662/CY7C43682
21
PRELIMINARY
Notes:
27. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 Read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been
read from the FIFO.
28. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
29. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition HIGH one CLKB cycle later than shown.
30. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been
read from the FIFO.
31. If Port B size is word or byte, t
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
32. t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then AEA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms
(continued)
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[29]
t
ENS
t
ENH
X1 Word in FIFO1
(X1+1)Words in FIFO1
CLKA
ENA
CLKB
AEB
ENB
Timing for AEB when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[27, 28]
t
PAE
t
PAE
t
ENH
t
ENS
t
SKEW2[32]
t
ENS
t
ENH
X2 Word in FIFO2
(X2+1)Words in FIFO2
CLKB
ENB
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)
[30, 31]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43682 | 16K x36 x2 Bidirectional Synchronous FIFO(16K x36 x2 雙向同步先進先出) |
| CY7C43633 | 512 x36 Unidirectional Synchronous FIFO w/ Bus Matching(512 x36 單向同步先進先出帶總線匹配) |
| CY7C43623 | 256 x36 Unidirectional Synchronous FIFO w/ Bus Matching(256 x36 單向同步先進先出帶總線匹配) |
| CY7C43643 | 1K x36 Unidirectional Synchronous FIFO w/ Bus Matching(1K x36 單向同步先進先出帶總線匹配) |
| CY7C43663 | 4K x36 Unidirectional Synchronous FIFO w/ Bus Matching(4K x36 單向同步先進先出帶總線匹配) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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