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參數(shù)資料
| 型號： | CY7C375i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128-宏單元閃速CPLD) |
| 中文描述： | UltraLogic 128宏單元CPLD的閃光（超邏輯的128 -宏單元閃速的CPLD） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 263K |
| 代理商： | CY7C375I |
CY7C375i
8
Switching Characteristics
Over the Operating Range
[13]
7C375i
–
125
Min.
7C375i
–
100
Min.
7C375i
–
83
7C374iL
–
83
Min.
7C375i
–
66
7C375iL
–
66
Min.
Parameter
Combinatorial Mode Parameters
t
PD
t
PDL
Input to Output Through Transparent Input
or Output Latch
[1]
t
PDLL
Input to Output Through Transparent Input
and Output Latches
[1]
t
EA
t
ER
Input to Output Disable
Input Registered/Latched Mode Parameters
t
WL
t
WH
t
IS
Input Register or Latch Set-Up Time
t
IH
Input Register or Latch Hold Time
t
ICO
Input Register Clock or Latch Enable to
Combinatorial Output
[1]
t
ICOL
Input Register Clock or Latch Enable to
Output Through Transparent Output
Latch
[1]
Ouptut Registered/Latched Mode Parameters
t
CO
t
S
Set-Up Time from Input to Clock or Latch
Enable
t
H
Register or Latch Data Hold Time
t
CO2
Output Clock or Latch Enable to Output
Delay (Through Memory Array)
[1]
t
SCS
Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
t
SL
Set-Up Time from Input Through Transpar-
ent Latch to Output Register Clock or Latch
Enable
t
HL
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
f
MAX1
Maximum Frequency with Internal Feed-
back (Least of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[9]
f
MAX2
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
), 1/(t
S
+ t
H
), or 1/t
CO
)
f
MAX3
Maximum Frequency with External Feed-
back (Lesser of 1/(t
CO
+ t
S
) and 1/(t
WL
+
t
WH
,
t
OH
–
t
IH
37x
Minus Input Register Hold Time for
7C37x
[9, 14]
Description
Max.
Max.
Max.
Max.
Unit
Input to Combinatorial Output
[1]
10
13
12
15
15
18
20
22
ns
ns
15
16
19
24
ns
Input to Output Enable
[1]
14
14
16
16
19
19
24
24
ns
ns
Clock or Latch Enable Input LOW Time
[9]
Clock or Latch Enable Input HIGH Time
[9]
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
14
16
19
24
16
18
21
26
ns
Clock or Latch Enable to Output
[1]
6.5
7
8
10
ns
ns
5.5
6
8
10
0
0
0
0
ns
ns
14
16
19
24
8
10
12
15
ns
10
12
15
20
ns
0
0
0
0
ns
125
100
83
66
MHz
158.3
143
125
100
MHz
83.3
76.9
62.5
50
MHz
Output Data Stable from Output Clock
0
0
0
0
ns
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C375 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C402 | 64 x 5 Cascadable FIFO(64 x 5位級聯(lián)型先進先出（FIFO）) |
| CY7C401 | 64 x 4 Cascadable FIFO(64 x 4 位級聯(lián)型先進先出（FIFO）) |
| CY7C403 | 64 x 4 Cascadable FIFO(64 x 4 位級聯(lián)型先進先出（FIFO）) |
| CY7C404 | 64 x 5 Cascadable FIFO(64 x 5位 級聯(lián)型先進先出（FIFO）) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C375I-125AC | 功能描述:IC CPLD 128 MACROCELL 160LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:Ultralogic™ 標準包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應商設備封裝:176-TQFP（24x24） 包裝:托盤 |
| CY7C375I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells CMOS Technology 5V 160-Pin TQFP |
| CY7C375I-66AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C375IL-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C385A1JC | 制造商:CYPRESS 功能描述:* |
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