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參數(shù)資料
| 型號： | CY7C375i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128-宏單元閃速CPLD) |
| 中文描述： | UltraLogic 128宏單元CPLD的閃光（超邏輯的128 -宏單元閃速的CPLD） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 263K |
| 代理商： | CY7C375I |
UltraLogic 128-Macrocell Flash CPLD
Functional Description
CY7C375i
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 1, 1998
Features
128 macrocells in eight logic blocks
128 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR) Flash technology
—JTAG Interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 125 MHz
—t
PD
= 10 ns
—t
S
= 5.5 ns
—t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 160-pin TQFP, CQFP, and PGA packages
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C375i is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
Logic Block Diagram
7C375i–1
PIM
INPUT
MACROCELL
CLOCK
INPUTS
INPUTS
4
4
36
16
16
36
LOGIC
BLOCK
A
36
16
16
36
16 I/Os
36
36
36
16
16
36
16
16
64
64
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
15
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
16
–I/O
31
I/O
32
–I/O
47
I/O
48
–I/O
63
I/O
112
–I/O
127
I/O
96
–I/O
111
I/O
80
–I/O
95
I/O
64
–I/O
79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
Selection Guide
7C375i–125
7C375i–100
7C375i–83
7C375iL–83
7C375i–66
7C375iL–66
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
Note:
1.
The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V
10
12
15
15
20
20
5.5
6
8
8
10
10
6.5
7
8
8
10
10
125
125
125
75
125
75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C375 | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128 宏單元閃速CPLD) |
| CY7C402 | 64 x 5 Cascadable FIFO(64 x 5位級聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C401 | 64 x 4 Cascadable FIFO(64 x 4 位級聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C403 | 64 x 4 Cascadable FIFO(64 x 4 位級聯(lián)型先進(jìn)先出（FIFO）) |
| CY7C404 | 64 x 5 Cascadable FIFO(64 x 5位 級聯(lián)型先進(jìn)先出（FIFO）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C375I-125AC | 功能描述:IC CPLD 128 MACROCELL 160LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultralogic™ 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| CY7C375I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells CMOS Technology 5V 160-Pin TQFP |
| CY7C375I-66AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C375IL-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C385A1JC | 制造商:CYPRESS 功能描述:* |
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