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參數(shù)資料
| 型號： | CY7C375i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD(超邏輯的128-宏單元閃速CPLD) |
| 中文描述： | UltraLogic 128宏單元CPLD的閃光（超邏輯的128 -宏單元閃速的CPLD） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 263K |
| 代理商： | CY7C375I |
CY7C375i
5
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i PLDs. Note that product term allocation is han-
dled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note,
“
An In-
troduction to In System Reprogramming with F
LASH
370i.
”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
CCIO
pins are connect-
Operating Range
ed to a 3.3V source, the input voltage levels are compatible
with both 5.0V and 3.3V systems, while the output voltage lev-
els are compatible with 3.3V systems. There will be an addi-
tional timing delay on all output buffers when operating in 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device
’
s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C371i is available from Cy-
press
’
s
Warp2
,
Warp2
Sim
, and
Warp3
software packag-
es. All of these products are based on the IEEE-standard
VHDL language. Cypress also actively supports third-party
design tools from companies such as Synopsys, Mentor
Graphics, Cadence, and Synario. Please refer to third-party
tool support for further information.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................
–
65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................
–
55
°
C to +125
°
C
Supply Voltage to Ground Potential................
–
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................
–
0.5V to +7.0V
DC Input Voltage ............................................
–
0.5V to +7.0V
DC Program Voltage..................................................... 12.5V
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Range
Ambient
Temperature
0
°
C to +70
°
C
V
CC
V
CCINT
5V
±
0.25V
V
CCIO
5V
±
0.25V
OR
3.3V
±
0.3V
5V
±
0.5V
OR
3.3V
±
0.3V
Commercial
Industrial
40
°
C to +85
°
C
5V
±
0.5V
Military
[2]
–
55
°
C to +125
°
C
5V
±
0.5V
Note:
2.
T
A
is the
“
instant on
”
case temperature.
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