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參數(shù)資料
| 型號(hào)： | CY7C371i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 32-Macrocell Flash CPLD(超邏輯的32 宏單元閃速 CPLD) |
| 中文描述： | UltraLogic 32宏單元CPLD的閃光（超邏輯的32個(gè)宏單元閃速的CPLD） |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | CY7C371I |
CY7C371i
6
Switching Characteristics
Over the Operating Range
[12]
Parameter
Combinatorial Mode Parameters
Input to Combinatorial Output
[1]
Description
7C371i
143
Min.
7C371i
110
Min.
7C371i
83
7C371iL
83
Min.
7C371i
66
7C371iL
66
Min.
Unit
Max.
Max.
Max.
Max.
t
PD
t
PDL
8.5
10
12
15
ns
Input to Output Through Transparent Input or
Output Latch
[1]
11.5
13
18
22
ns
t
PDLL
Input to Output Through Transparent Input
and Output Latches
[1]
Input to Output Enable
[1]
13.5
15
20
24
ns
t
EA
t
ER
Input Registered/Latched Mode Parameters
t
WL
t
WH
t
IS
Input Register or Latch Set-Up Time
t
IH
Input Register or Latch Hold Time
t
ICO
Input Register Clock or Latch Enable to Com-
binatorial Output
[1]
13
14
19
24
ns
Input to Output Disable
13
14
19
24
ns
Clock or Latch Enable Input LOW Time
[8]
Clock or Latch Enable Input HIGH Time
[8]
2.5
3
4
5
ns
2.5
3
4
5
ns
2
2
3
4
ns
2
2
3
4
ns
12
14
19
24
ns
t
ICOL
Input Register Clock or Latch Enable to Out-
put Through Transparent Output Latch
[1]
Output Registered/Latched Mode Parameters
Clock or Latch Enable to Output
[1]
14
16
21
26
ns
t
CO
t
S
6
6.5
8
10
ns
Set-Up Time from Input to Clock or Latch
Enable
5
6
8
10
ns
t
H
t
CO2
Register or Latch Data Hold Time
0
0
0
0
ns
Output Clock or Latch Enable to Output Delay
(Through Memory Array)
[1]
12
14
19
24
ns
t
SCS
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
7
9
12
15
ns
t
SL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch En-
able
9
10
12
15
ns
t
HL
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
0
0
0
0
ns
f
MAX1
Maximum Frequency with Internal Feedback
(Least of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[8]
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
WL
+
t
WH
), 1/(t
S
+ t
H
), or 1/t
CO
)
[8]
Maximum Frequency with external feedback
(Lesser of 1/(t
CO
+ t
S
) and 1/(t
WL
+ t
WH
))
[8]
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x
[8,13]
143
111
83.3
66.6
MHz
f
MAX2
166.7
153.8
100
83.3
MHz
f
MAX3
91
80
50
41.6
MHz
t
OH
-t
IH
37x
0
0
0
0
ns
Notes:
12. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C371I-110AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 111MHz 5V 44-Pin TQFP 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 111MHz CMOS Technology 5V 44-Pin TQFP |
| CY7C371I-110AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C371I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz CMOS Technology 5V 44-Pin TQFP 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz 5V 44-Pin TQFP |
| CY7C371I-66JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C371I-83JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 83.3MHz CMOS Technology 5V 44-Pin PLCC |
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