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參數(shù)資料
| 型號： | CY7C372 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 64-Macrocell Flash CPLD(超邏輯的64-宏單元閃速CPLD) |
| 中文描述： | UltraLogic 64宏單元CPLD的閃光（超邏輯的64 -宏單元閃速的CPLD） |
| 文件頁數(shù)： | 1/1頁 |
| 文件大小： | 41K |
| 代理商： | CY7C372 |
For new designs see CY7C372i
UltraLogic 64-Macrocell Flash CPLD
fax id: 6127
CY7C372
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1992 – Revised April 20, 1998
Features
64 macrocells in four logic blocks
32 I/O pins
6 dedicated inputs including 2 clock pins
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 125 MHz
—t
PD
= 10 ns
—t
S
= 5.5 ns
—t
CO
= 6.5 ns
Electrically alterable Flash technology
Available in 44-pin PLCC and CLCC packages
Pin compatible with the CY7C371
Functional Description
The CY7C372 is a Flash erasable Complex Programmable
Logic Device (CPLD) and is part of the F
LASH
370
family of
high-density, high-speed CPLDs. Like all members of the
F
LASH
370 family, the CY7C372 is designed to bring the ease
of use and high performance of the 22V10 to high-density
CPLDs.
The 64 macrocells in the CY7C372 are divided between four
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370 architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the F
LASH
370 family, the CY7C372 is rich
in I/O resources. Every two macrocells in the device feature an
associated I/O pin, resulting in 32 I/O pins on the CY7C372. In
addition, there are four dedicated inputs and two input/clock
pins.
Finally, the CY7C372 features a very simple timing model. Un-
like other high-density CPLD architectures, there are no hid-
den speed delays such as fanout effects, interconnect delays,
or expander delays. Regardless of the number of resources
used or the type of application, the timing parameters on the
CY7C372 remain the same.
7c372–1
PIM
INPUT
MACROCELLS
CLOCK
INPUTS
INPUTS
LOGIC
BLOCK
B
LOGIC
BLOCK
C
2
2
36
16
16
36
16
16
LOGIC
BLOCK
D
36
16
16
36
2
4
INPUT/CLOCK
MACROCELLS
LOGIC
BLOCK
A
I/O
0
I/O
7
I/O
8
I/O
15
I/O
24
I/O
31
I/O
16
I/O
23
8 I/Os
8 I/Os
8 I/Os
8 I/Os
Selection Guide
7C372-125
10
5.5
6.5
280
7C372-100
12
6
6.5
250
7C372-83
15
8
8
250
300
7C372-66
20
10
10
250
300
7C372L-66
20
10
10
125
Maximum Propagation Delay, t
PD
(ns)
Minimum Set-up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Maximum Supply
Current, I
CC
(mA)
Commercial
Military/Industrial
Shaded areas contain preliminary information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C373i | UltraLogic 64-Macrocell Flash CPLD(超邏輯的64 宏單元閃速 CPLD) |
| CY7C374I-66JC | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-83YMB | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-100AC | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-100JC | UltraLogic 128-Macrocell Flash CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C372-100JC | 制造商:Cypress Semiconductor 功能描述:FLASH PLD, 16 ns, PQCC44 |
| CY7C3721-66JI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C372I-100JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 44-Pin PLCC |
| CY7C372I-125JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 44-Pin PLCC |
| CY7C372I-66JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC |
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