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參數(shù)資料
| 型號： | CY7C371i |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 32-Macrocell Flash CPLD(超邏輯的32 宏單元閃速 CPLD) |
| 中文描述： | UltraLogic 32宏單元CPLD的閃光（超邏輯的32個宏單元閃速的CPLD） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 190K |
| 代理商： | CY7C371I |
UltraLogic 32-Macrocell Flash CPLD
CY7C371i
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 1, 1998
Features
32 macrocells in two logic blocks
32 I/O pins
5 dedicated inputs including 2 clock pins
In-System Reprogrammable (ISR) Flash technology
—JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 143 MHz
—t
PD
= 8.5 ns
—t
S
= 5 ns
—t
CO
= 6 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 44-pin PLCC, and TQFP packages
Pin compatible with the CY7C372i
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C371i is de-
signed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term al-
locator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the F
LASH
370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an as-
sociated I/O pin, resulting in 32 I/O pins on the CY7C371i. In
addition, there are three dedicated inputs and two input/clock
pins.
PIM
3
INPUT
MACROCELLS
2
CLOCK
INPUTS
INPUTS
LOGIC
BLOCK
A
LOGIC
BLOCK
B
2
2
36
16
16
36
16 I/Os
16 I/Os
16
16
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
15
I/O
16
–I/O
31
Logic Block Diagram
7c371i–1
Selection Guide
7C371i-143
7C371i-110
7C371i-83
7C371iL-83
7C371i-66
7C371iL-66
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply
Current, I
CC
(mA)
Note:
1.
The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
8.5
10
12
12
15
15
5
6
8
8
10
10
6
6.5
8
8
10
10
Comm./Ind.
75
75
75
45
75
45
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| CY7C373i | UltraLogic 64-Macrocell Flash CPLD(超邏輯的64 宏單元閃速 CPLD) |
| CY7C374I-66JC | UltraLogic 128-Macrocell Flash CPLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C371I-110AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 111MHz 5V 44-Pin TQFP 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 111MHz CMOS Technology 5V 44-Pin TQFP |
| CY7C371I-110AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C371I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz CMOS Technology 5V 44-Pin TQFP 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz 5V 44-Pin TQFP |
| CY7C371I-66JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C371I-83JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 83.3MHz CMOS Technology 5V 44-Pin PLCC |
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