參數(shù)資料
型號： CY7C1487V33-133BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 2M x 36/4M x 18/1M x 72 Flow-through SRAM
中文描述： 1M X 72 CACHE SRAM, 6.5 ns, PBGA209
封裝： 14 X 22 MM, 1.76 MM HEIGHT, PLASTIC, FBGA-209
文件頁數(shù)： 17/30頁
文件大?。?/td> 638K
代理商： CY7C1487V33-133BGC
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 17 of 30
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Department Number (27:25)
Voltage (28&24)
Architecture (23:21)
Memory Type (20:18)
Device Width (17:15)
Device Density (14:12)
Cypress JEDEC ID (11:1)
x 18
000
101
00
000
001
010
100
0000011
0100
1
x36
000
101
00
000
001
100
100
x72
000
101
00
000
001
110
100
Description
Reserved for version number
Department number
Architecture type
Defines type of memory
Defines width of the SRAM. x36 or x18
Defines the density of the SRAM
Allows unique identification of SRAM vendor
0000011
0100
1
0000011
0100
1
ID Register Presence (0)
Indicate the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size (x18)
3
1
32
TBD
Bit Size (x36)
3
1
32
TBD
Bit Size (x72)
3
1
32
TBD
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD 100
011
RESERVED
RESERVED
BYPASS
101
110
111
Boundary Scan Order (2M x 36)
Bit #
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit #
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Boundary Scan Order (2M x 36)
(continued)
Bit #
TBD
Signal
Name
TBD
Bump
ID
TBD
Bit #
TBD
Signal
Name
TBD
Bump
ID
TBD
相關(guān)PDF資料
PDF描述
CY7C1483V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-100AC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-100BGC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-100BZC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-117AC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
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