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參數(shù)資料
| 型號(hào)： | CY7C1487V33-133BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 6.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, PLASTIC, FBGA-209 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 638K |
| 代理商： | CY7C1487V33-133BGC |
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PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 10 of 30
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation
“
sleep
”
mode. Two
clock cycles are required to enter into or exit from this
“
sleep
”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the
“
sleep
”
mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the
“
sleep
”
mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ
“
sleep
”
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
1
X
1
0
X
1
X
1
X
1
X
X
1
X
1
1
X
1
X
X
1
1
1
1
1
0
1
1
1
1
X
1
1
1
1
1
X
0
0
1
1
X
0
1
0
X
X
X
X
X
X
X
X
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Cycle Descriptions
(continued)
[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE
3
CE
2
CE
1
ADSP
ADSC
ADV
OE
DQ
Write
Interleaved Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
10
11
00
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > V
DD
–
0.2V
Min.
Max.
TBD
Unit
mA
t
ZZS
ZZ > V
DD
–
0.2V
2t
CYC
ns
t
ZZREC
ZZ < 0.2V
2t
CYC
ns
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| CY7C1483V33 | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-100AC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-100BGC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
| CY7C1483V33-100BZC | 2M x 36/4M x 18/1M x 72 Flow-through SRAM |
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