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參數(shù)資料
| 型號： | CY7C1471V25-100AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| 中文描述： | 2M X 36 ZBT SRAM, 8.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 373K |
| 代理商： | CY7C1471V25-100AXC |
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PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 16 of 30
1.8V TAP AC Test Conditions
Input pulse levels.....................................0.2V to V
DDQ
– 0.2
Input rise and fall time..................................................... 1 ns
Input timing reference levels...........................................0.9V
Output reference levels...................................................0.9V
Test load termination supply voltage...............................0.9V
1.8V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
0.9V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 2.375 to 2.625 unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
V
OH2
Output HIGH Voltage
Test Conditions
Min.
2.0
2.1
1.6
Max.
Unit
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
OL1
V
OL2
Output LOW Voltage
Output LOW Voltage
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.2
0.2
V
IH
Input HIGH Voltage
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.7
0.36
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
CY7C1471V25
(2MX36)
000
01011
001001
CY7C1473V25
(4MX18)
000
01011
001001
CY7C1475V25
(1MX72)
000
01011
001001
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
100100
00000110100
010100
00000110100
110100
00000110100 Allows unique identification of SRAM
vendor
1
Indicates the presence of an ID register
Defines width and density
1
1
Note:
12.All voltages referenced to V
SS
(GND).
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1471V25-133BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V25-133BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1473V25-133BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V25-100BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
| CY7C1471V25-100BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1471V25-100AXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1471V25-100BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1471V25-133AXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (2Mx36) 2.5v 133MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1471V25-133AXCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 6.5NS 100TQFP - Bulk |
| CY7C1471V25-133AXCT | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 2.5V NoBL FT 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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