參數(shù)資料
型號(hào): CY7C1471V25-100AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述: 2M X 36 ZBT SRAM, 8.5 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù): 11/30頁(yè)
文件大小: 373K
代理商: CY7C1471V25-100AXC
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 11 of 30
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
None
None
None
None
External
CE
1
H
X
X
X
L
CE
2
CE
3
X
X
L
X
H
ZZ
L
L
L
L
L
ADV/LD
L
L
L
H
L
WE
X
X
X
X
H
BW
X
X
X
X
X
X
OE
X
X
X
X
L
CEN
L
L
L
L
L
CLK
L->H
L->H
L->H
L->H
L->H Data Out (Q)
DQ
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
X
H
X
X
L
Tri-State
Tri-State
Tri-State
Tri-State
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
None
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
X
L->H
X
-
Tri-State
Truth Table for Read/Write
[2, 3, 9]
Function (CY7C1471V25)
WE
H
L
L
L
L
L
L
BW
A
X
H
L
H
H
H
L
BW
B
X
H
H
L
H
H
L
BW
C
X
H
H
H
L
H
L
BW
D
X
H
H
H
H
L
L
Read
Write No bytes written
Write Byte A – (DQ
A
and DQP
A
)
Write Byte B – (DQ
B
and DQP
B
)
Write Byte C – (DQ
C
and DQP
C
)
Write Byte D – (DQ
D
and DQP
D
)
Write All Bytes
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW
X
= L signifies at least one Byte Write Select is active, BW
X
= Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
X
= Tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW
X
is valid Appropriate write will be done based on which byte write is active.
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CY7C1471V25-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-133BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1471V25-100AXI 制造商:Cypress Semiconductor 功能描述:
CY7C1471V25-100BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1471V25-133AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (2Mx36) 2.5v 133MHz 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1471V25-133AXCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 6.5NS 100TQFP - Bulk
CY7C1471V25-133AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx36 2.5V NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray