參數(shù)資料
型號(hào): CY7C1464AV33
廠商: Cypress Semiconductor Corp.
英文描述: 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
中文描述: 36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM架構(gòu)的總線延遲(帶總線延遲結(jié)構(gòu)的36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM)
文件頁數(shù): 20/27頁
文件大?。?/td> 469K
代理商: CY7C1464AV33
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Document #: 38-05353 Rev. *D
Page 20 of 27
Switching Waveforms
Read/Write/Timing
[24, 25, 26]
Notes:
24.For this waveform ZZ is tied low.
25.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH,CE
is HIGH or CE
is LOW or CE
is HIGH.
26.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
x
ADV/LD
t
AH
t
AS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE
UNDEFINED
Q(A6)
Q(A4+1)
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CY7C1462AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
CY7C1472V33-167AXI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
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CY7C1472V33-200AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
CY7C1472V33-200BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
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