參數(shù)資料
型號: CY7C1462AV33
廠商: Cypress Semiconductor Corp.
英文描述: 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
中文描述: 36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM架構(gòu)的總線延遲(帶總線延遲結(jié)構(gòu)的36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM)
文件頁數(shù): 13/27頁
文件大小: 469K
代理商: CY7C1462AV33
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Document #: 38-05353 Rev. *D
Page 13 of 27
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels ................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V
DD
= 3.135V to 3.6V unless otherwise noted)
[11]
Parameter
Description
V
OH1
Output HIGH Voltage
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
OH2
Output HIGH Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
[12]
Architecture/Memory Type(23:18)
CY7C1460AV33
(1M ×36)
000
01011
001000
CY7C1462AV33
(2M ×18)
000
01011
001000
CY7C1464AV33
(512K ×72)
000
01011
001000
Description
Describes the version number.
Reserved for Internal Use
Defines memory type and archi-
tecture
Defines width and density
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
100111
00000110100
010111
00000110100
110111
00000110100
ID Register Presence Indicator (0)
1
1
1
Notes:
11. All voltages referenced to V
(GND).
12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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