參數(shù)資料
型號: CY7C1462AV25
廠商: Cypress Semiconductor Corp.
英文描述: 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
中文描述: 36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM架構(gòu)的總線延遲(帶總線延遲結(jié)構(gòu)的36兆位(1米x 36/2M x 18/512K × 72)流水線的SRAM)
文件頁數(shù): 17/27頁
文件大小: 465K
代理商: CY7C1462AV25
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 17 of 27
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +3.6V
Supply Voltage on V
DDQ
Relative to GND ......–0.5V to +V
DD
DC to Outputs in Tri-State................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[14, 15]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
2.5V –5%/+5%
1.7V to
V
DD
DC Electrical Characteristics
Over the Operating Range
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
2.0
1.6
Max.
2.625
V
DD
1.9
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
for 2.5V I/O
for 1.8V I/O
for 2.5V I/O, I
OH
=
1.0 mA
for 1.8V I/O, I
OH
= –100
μ
A
for 2.5V I/O, I
OL
=
1.0 mA
for 1.8V I/O, I
OL
= 100
μ
A,
for 2.5V I/O
for 1.8V I/O
for 2.5V I/O
for 1.8V I/O
GND
V
I
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.2
V
IH
Input HIGH Voltage
[14]
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.7
0.36
5
V
IL
Input LOW Voltage
[14]
I
X
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
SS
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
Input = V
DD
Input = V
SS
Input = V
DD
5
Input Current of ZZ
–5
30
5
435
385
335
185
I
OZ
I
DD
Output Leakage Current GND
V
I
V
DDQ,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
–5
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
All speed grades
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = f
MAX
=
1/t
CYC
Max. V
DD
, Device Deselected,
V
IN
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
Max. V
DD
, Device Deselected,
V
IN
0.3V or V
IN
> V
DDQ
0.3V,
f = f
MAX
= 1/t
CYC
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
I
SB2
All speed grades
120
mA
I
SB3
All speed grades
160
mA
I
SB4
All speed grades
135
mA
Notes:
14.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC)> –2V (Pulse width less than t
CYC
/2).
15.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
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