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參數(shù)資料
| 型號： | CY7C1399B-12ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 3.3V Static RAM |
| 中文描述： | 32K X 8 CACHE SRAM, 12 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, TSOP1-28 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 151K |
| 代理商： | CY7C1399B-12ZC |
CY7C1399B
Document #: 38-05071 Rev. *C
Page 4 of 10
Switching Characteristics
Over the Operating Range
[6]
1399B-10
Min.
1399B-12
Min.
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[9, 10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
6.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and capacitance C
= 30 pF.
7.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
8.
t
, t
, t
are specified with C
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
Max.
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[7, 8]
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
3
3
10
5
12
5
0
0
5
5
3
3
5
6
0
0
10
12
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9]
WE HIGH to Low Z
[7]
10
8
7
0
0
7
5
0
12
8
8
0
0
8
7
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
3
3
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1399B-12ZCT | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- FAST ASYNCH SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1399B-12ZXC | 功能描述:IC SRAM 256KBIT 12NS 28TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| CY7C1399B-12ZXCT | 功能描述:IC SRAM 256KBIT 12NS 28TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1399B-15VC | 功能描述:IC SRAM 256KBIT 15NS 28SOJ RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| CY7C1399B-15VCT | 制造商:Rochester Electronics LLC 功能描述:256K (32K X 8)- FAST ASYNCH SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
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