參數(shù)資料
型號: CY7C1386C
廠商: Cypress Semiconductor Corp.
元件分類: DRAM
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
中文描述: 18 MB的(為512k × 36/1M × 18)流水線雙氰胺同步靜態(tài)存儲器
文件頁數(shù): 26/34頁
文件大?。?/td> 554K
代理商: CY7C1386C
CY7C1386C
CY7C1387C
Document #: 38-05239 Rev. *B
Page 26 of 34
Switching Waveforms
Read Cycle Timing
[22]
Notes:
22.On this diagram, when CE is LOW: CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
23.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
X
LOW.
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,BW
Data Out (DQ)
High-Z
tDOH
tCO
ADV
tOEHZ
tCO
Single READ
BURST READ
tOEV
tOELZ
tCHZ
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A2 + 3)
A2
A3
Deselect
cycle
Burst continued with
new base address
ADV suspends burst
DON’T CARE
UNDEFINED
X
CLZ
t
相關(guān)PDF資料
PDF描述
CY7C1386C-225BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-225BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BG 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BGC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1386C-167BZC 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
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