參數(shù)資料
型號: CY7C1382CV25
廠商: Cypress Semiconductor Corp.
英文描述: 512K x 36/1M x 18 Pipelined SRAM
中文描述: 為512k × 36/1M × 18流水線的SRAM
文件頁數(shù): 9/33頁
文件大小: 537K
代理商: CY7C1382CV25
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 9 of 33
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation
sleep
mode. Two clock
cycles are required to enter into or exit from this
sleep
mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the
sleep
mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the
sleep
mode.
CEs, ADSP, and ADSC must remain inactive for the duration
of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Sequence
First
Address
A
[1:0]]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
DDZZ
Sleep mode stand-
by current
ZZ
>
V
DD
0.2V
60
mA
t
ZZS
Device operation to
ZZ
ZZ
>
V
DD
0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ
<
0.2V
2t
CYC
ns
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