參數(shù)資料
型號: CY7C1382CV25
廠商: Cypress Semiconductor Corp.
英文描述: 512K x 36/1M x 18 Pipelined SRAM
中文描述: 為512k × 36/1M × 18流水線的SRAM
文件頁數(shù): 22/33頁
文件大小: 537K
代理商: CY7C1382CV25
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 22 of 33
Switching Characteristics
Over the Operating Range
[15, 16, 17]
-250
-225
-200
-167
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CO
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Shaded areas contain preliminary information.
Description
Min.
4.0
1.7
1.7
1.2
0.3
Max.
Min.
4.4
2.0
2.0
1.4
0.4
Max.
Min.
5
2.0
2.0
1.4
0.4
Max.
Min.
6
2.2
2.2
1.5
0.5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW
x
Set-up Before CLK Rise
BWE, GW, BW
x
Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-up
Chip Enable Hold After CLK Rise
Clock to High-Z
[16]
Clock to Low-Z
[16]
OE HIGH to Output High-Z
[16, 17]
OE LOW to Output Low-Z
[16, 17]
OE LOW to Output Valid
[16]
2.6
2.8
3.0
3.4
1.0
1.2
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.0
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.3
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
2.6
2.8
3.0
3.4
1.0
1.0
1.3
1.3
2.6
2.8
3.0
3.4
0
0
0
0
2.6
2.8
3.0
3.4
Notes:
15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
16. t
, t
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-
state voltage.
17. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
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