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參數(shù)資料
| 型號(hào)： | CY7C1382CV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM |
| 中文描述： | 為512k × 36/1M × 18流水線的SRAM |
| 文件頁數(shù)： | 6/33頁 |
| 文件大小： | 537K |
| 代理商： | CY7C1382CV25 |
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CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 6 of 33
Pin Definitions
Name
I/O
Input-
Description
A0
A1
A
BWa
BWb
BWc
BWd
GW
Synchronous
Address Inputs used to select one of the address locations
. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
,
and
CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW
. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
Clock Input
. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used
in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ig-
nored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and CE
3
to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and
CE
2
to select/deselect the device.
(TQFP Only)
Output Enable, asynchronous input, active LOW
. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK
. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK
.
When asserted LOW, A is captured in the address registers. A
[1:0]
are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK
.
When asserted LOW, A
[x:0]
is captured in the address registers. A
[1:0]
are also
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
Selects Burst Order
. When tied to GND selects linear burst sequence. When
tied to V
DDQ
or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ
“
sleep
”
Input
. This active HIGH input places the device in a non-time
critical
“
sleep
”
condition with data integrity preserved.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
[X]
during the previous clock
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx
are
placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP
a,b,c, and d are 1 bit wide.
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of
TCK. (BGA Only)
Serial data-in to the JTAG circuit
. Sampled on the rising edge of TCK.(BGA
Only)
BWE
Input-
Synchronous
Input-Clock
CLK
CE
1
Input-
Synchronous
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
3
OE
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
MODE
Input-Pin
ZZ
Input-
Asynchronous
I/O-
Synchronous
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
TDO
JTAG serial output
Synchronous
JTAG serial input
Synchronous
TDI
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