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參數(shù)資料
| 型號： | CY7C1372D-200BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| 中文描述： | 1M X 18 ZBT SRAM, 3 ns, PBGA119 |
| 封裝： | (14 X 22 X 2.4) MM, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 22/30頁 |
| 文件大?。?/td> | 344K |
| 代理商： | CY7C1372D-200BGI |
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PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 22 of 30
Switching Characteristics
Over the Operating Range
[23, 24]
Parameter
t
Power[19]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Shaded areas contain advance information.
Notes:
19.This part has a voltage regulator internally; t
Power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
20.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
23.Timing reference is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
24.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
-250
-225
-200
-167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the first access read or write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.0
4.4
5
6
ns
MHz
ns
ns
250
225
200
167
1.7
1.7
2.0
2.0
2.0
2.0
2.2
2.2
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
[20, 21, 22]
Clock to Low-Z
[20, 21, 22]
OE HIGH to Output High-Z
[20, 21, 22]
OE LOW to Output Low-Z
[20, 21, 22]
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.3
1.3
2.6
2.8
3.0
3.4
1.0
1.0
1.3
1.3
2.6
2.8
3.0
3.4
0
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
x
Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
x
Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1372D-200BZC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-200BZI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-225AXC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-225AXI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C1372DV25-167AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372DV25-167AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372DV25-167BGI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372DV25-167BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372DV25-167BZXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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