參數(shù)資料
型號: CY7C1372D-200BGI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
中文描述: 1M X 18 ZBT SRAM, 3 ns, PBGA119
封裝: (14 X 22 X 2.4) MM, PLASTIC, BGA-119
文件頁數(shù): 21/30頁
文件大小: 344K
代理商: CY7C1372D-200BGI
PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 21 of 30
Note:
18.Tested initially and after any design or process change that may affect these parameters.
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
All speed grades
80
mA
Electrical Characteristics
Over the Operating Range
(continued)
[16, 17]
Parameter
Description
Test Conditions
Min.
Max.
Unit
Capacitance
[18]
Parameter
C
IN
C
CLK
C
I/O
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V.
V
DDQ
= 2.5V
TQFP
Package
5
5
5
BGA
Package
8
8
8
fBGA
Package
9
9
9
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
[18]
Parameter
Θ
JA
Description
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
TQFP
Package
31
BGA
Package
45
fBGA
Package
46
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Θ
JC
6
7
3
°
C/W
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
1ns
1ns
(c)
OUTPUT
R = 1667
R = 1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
1ns
1ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
AC Test Loads and Waveforms
相關PDF資料
PDF描述
CY7C1372D-200BZC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-200BZI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-225AXC 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1372D-225AXI 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
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