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參數(shù)資料
| 型號(hào)： | CY7C1372D-200BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| 中文描述： | 1M X 18 ZBT SRAM, 3 ns, PBGA119 |
| 封裝： | (14 X 22 X 2.4) MM, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 10/30頁(yè) |
| 文件大?。?/td> | 344K |
| 代理商： | CY7C1372D-200BGI |
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PRELIMINARY
CY7C1370D
CY7C1372D
Document #: 38-05555 Rev. *A
Page 10 of 30
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370D/CY7C1372D incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1370D/CY7C1372D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS
) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to V
DD
through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Partial Write Cycle Description
[1, 2, 3, 8]
Function (CY7C1370D)
WE
H
L
BW
d
X
H
BW
c
X
H
BW
b
X
H
BW
a
X
H
Read
Write – No bytes written
Write Byte a – (DQ
a
and
DQP
a
)
Write Byte b – (DQ
b
and
DQP
b
)
Write Bytes b, a
Write Byte c – (DQ
c
and
DQP
c
)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
d
and
DQP
d
)
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Function (CY7C1372D)
WE
H
L
L
L
L
BW
b
x
H
H
L
L
BW
a
x
H
L
H
L
Read
Write – No Bytes Written
Write Byte a – (DQ
a
and
DQP
a
)
Write Byte b – (DQ
b
and
DQP
b
)
Write Both Bytes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1372D-200BZC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-200BZI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-225AXC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-225AXI | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
| CY7C1372D-225BGC | 18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1372DV25-167AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372DV25-167AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372DV25-167BGI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372DV25-167BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372DV25-167BZXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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